Texas Instruments MuxIt-EVM Evaluation Module MUXIT-EVM MUXIT-EVM Datenbogen

Serializer Board

2-3

EVM Hardware Contents

other can be remotely powered through the J2 connector. The GND
connection between the two boards can be established by installing
A1:JMP-11 and A2:JMP-3 on the deserializer. The VCC connection between
the two can be established by installing A1:JMP-12 and A2:JMP-2 on the
deserializer. These jumpers

 

can also be used when V

CC

 and GND are

provided through a cable instead of the adapter header, and the serializer and
deserializer boards are located several meters away from each other. These
jumpers must be removed when powering the serializer and deserializer
boards from separate power supplies. The following table shows the serializer
board jumper configurations.

Table 2–1. Serializer Board Jumpers

A1:JMP–1

One position

Installed

This jumper can be used when a single–ended clock is input to the
SN65LVDS150 PLL, A1:U1, or removed when a differential clock is input.

A1:JMP–2

Two position

VCC

Enables the A1:U1, SN65LVDS150 PLL.
VCC = Enabled; GND = Disabled.

A1:JMP–3

Two position

VCC

Enables the link clock reference output of the A1:U1.
VCC = Enabled; GND = Disabled.

A1:JMP–4

Two position

VCC

Enables the A1:U2, SN65LVDS151 serializer-transmitter.
VCC = Enabled; GND = Disabled.

A1:JMP–5

Two position

ExtVCC5

Input bias for all three SN65LVDS151 data inputs.
ExtVCC5 = voltage level on Test Point 2 (A1:TP2);
VCC = Power Plane of board.

A1:JMP–6

Two position

VCC

Enables the A1:U3, SN65LVDS151 serializer-transmitter.
VCC = Enabled; GND = Disabled.

A1:JMP–7

Two position

VCC

Enables the link clock output of the A1:U3.
VCC = Enabled; GND = Disabled.

A1:JMP–8

Two position

VCC

Enables the A1:U4, SN65LVDS151 serializer-transmitter.
VCC = Enabled; GND = Disabled.

A1:JMP–11

One position

Installed

When installed, remote ground, A1:J2 pin 2, is connected to the serializer
board GND plane.

A1:JMP–12

One position

Installed

When installed, remote VCC, A1:J2 pin 1, is connected to the serializer
board VCC plane.

The basic operation is supported by A1:U3. The inputs are parallel data on
A1:P2 and clock on A1:J3 and A1:J4. A1:J3 and A1:J4 are the clock inputs
used for each operation. The differential outputs of A1:U3 are on A1:J2
pins 4–5 and 7–8, the clock and data respectively.

For cascaded operation, parallel data from A1:P1 and A1:P2 are input to
A1:U2 and A1:U3. The data is output on the same clock and data lines as in
the basic operation, A1:J2 pins 4–5 and pins 7–8, respectively.

Parallel operation is achieved with inputs A1:P2 and A1:P3 to devices A1:U3
and A1:U4. The output LVDS links are A1:J2 pins 4–5 for the clock, pins 7–8
for data, and pins 10–11 also for data.