Texas Instruments MuxIt-EVM Evaluation Module MUXIT-EVM MUXIT-EVM Datenbogen

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Deserializer Board
2-5
EVM Hardware Contents
Figure 2–2. Serializer Board
2.2
Deserializer Board
The deserializer board (P/N 6422796A) uses three SN65LVDS152
receiver-deserializers (A2:U2–U4) and a SN65LVDS150 PLL frequency
multiplier (A2:U1) to accept the serialized data and clock signals and convert
this serialized data stream back to the original parallel single-ended outputs.
A block diagram and photograph of the deserializer board is provided in
Figures 2–3 and 2–4, respectively.
2.2.1
Clock and Data Input Signals
The input signals are all LVDS. They are the same three output signals from
the Serializer: LCI+/LCI–, CASCADE_DI+/CASCADE_DI–, and SE-
RIAL_DI+/SERIAL_DI–. LCI is input into A2:U1, CASCADE_DI is input into
A2:U2, and SERIAL_DI is input into A2:U4.
2.2.2
Output Signals
The data and clock output signals provided on connectors A2:P1 through
A2:P3 are LVTTL signals. The output clock signal is provided on DCO of
A2:P1, A2:P2, and A2:P3 and any of the three can be used. Each output
connector is a 2x10 header. The side closest to the components is connected
to a resistor in series with the outputs of the SN65LVDS152 devices. The side
of the connector closest to the edge of the board is connected to GND.
2.2.3
Power Supply
The following table shows the deserializer board jumper configurations. Refer
to section 2.1.3 for power supply information.