Texas Instruments DS100BR111EVK Evaluation Module DS100BR111EVK/NOPB DS100BR111EVK/NOPB Datenbogen
Produktcode
DS100BR111EVK/NOPB
SNLS338E – JANUARY 2011 – REVISED FEBRUARY 2013
APPLICATIONS INFORMATION
4-Level Input Configuration Guidelines
The 4-level input pins utilize a resistor divider to help set the 4 valid levels. There is an internal 30K pull-up and a
60K pull-down connected to the package pin. These resistors, together with the external resistor connection
combine to achieve the desired voltage level. Using the 1K pull-up, 1K pull-down, no connect, and 20K pull-down
provide the optimal voltage levels for each of the four input states.
60K pull-down connected to the package pin. These resistors, together with the external resistor connection
combine to achieve the desired voltage level. Using the 1K pull-up, 1K pull-down, no connect, and 20K pull-down
provide the optimal voltage levels for each of the four input states.
Table 5. 4-Level Input Voltage
Level
Setting
3.3V Mode
2.5V Mode
0
01K to GND
0.1 V
0.08 V
R
20K to GND
0.33 * V
IN
0.33 * V
DD
F
FLOAT
0.67 * V
IN
0.67 * V
DD
1
1K to V
DD
/V
IN
V
IN
- 0.05V
V
IN
- 0.04V
•
Typical 4-Level Input Thresholds
–
–
Level 1 - 2 = 0.2 V
IN
or V
DD
–
Level 2 - 3 = 0.5 V
IN
or V
DD
–
Level 3 - 4 = 0.8 V
IN
or V
DD
In order to minimize the startup current associated with the integrated 2.5V regulator the 1K pull-up / pull-down
resistors are recommended. If several 4 level inputs require the same setting, it is possible to combine two or
more 1K resistors into a single lower value resistor. As an example; combining two inputs with a single 500
resistors are recommended. If several 4 level inputs require the same setting, it is possible to combine two or
more 1K resistors into a single lower value resistor. As an example; combining two inputs with a single 500
Ω
resistor is a good way to save board space.
10G-KR Configuration Guidelines
When configured in "KR Mode", using either the VOD_SEL pin setting or SMBus register control, the
DS100BR111 is designed to operate transparently within a KR backplance channel environment. Installing a
DS100 repeater within the KR backplane channel splits the total channel attenuation into two parts. Ideally the
repeater can be placed near the middle of the channel maximizing the signal to noise ratio across the
bidirectional interface.
DS100BR111 is designed to operate transparently within a KR backplance channel environment. Installing a
DS100 repeater within the KR backplane channel splits the total channel attenuation into two parts. Ideally the
repeater can be placed near the middle of the channel maximizing the signal to noise ratio across the
bidirectional interface.
In order to maximize the 10G-KR solution space, the 802.3ap specification calls for an optimization of the
transmit signal conditioning coefficients based on feedback for the KR receiver. Setting the DS100BR111 active
CTLE to compensate for the channel loss from each of the KR transmitters will reduce the transmit and receive
equalization settings required on the KR physical layer devices. This central location keeps a larger S/N raito at
all points in the channel, extending the available solution space and increasing the overall margin of almost any
channel.
transmit signal conditioning coefficients based on feedback for the KR receiver. Setting the DS100BR111 active
CTLE to compensate for the channel loss from each of the KR transmitters will reduce the transmit and receive
equalization settings required on the KR physical layer devices. This central location keeps a larger S/N raito at
all points in the channel, extending the available solution space and increasing the overall margin of almost any
channel.
PCB Layout Guidelines
The CML inputs and outputs have been optimized to work with interconnects using a controlled differential
impedance of 85 - 100
impedance of 85 - 100
Ω
. It is preferable to route differential lines exclusively on one layer of the board,
particularly for the input traces. The use of vias should be avoided if possible. If vias must be used, they should
be used sparingly and must be placed symmetrically for each side of a given differential pair. Whenever
differential vias are used the layout must also provide for a low inductance path for the return currents as well.
Route the differential signals away from other signals and noise sources on the printed circuit board. See
be used sparingly and must be placed symmetrically for each side of a given differential pair. Whenever
differential vias are used the layout must also provide for a low inductance path for the return currents as well.
Route the differential signals away from other signals and noise sources on the printed circuit board. See
AN-1187 for additional information on WQFN packages.
Different transmission line topologies can be used in various combinations to achieve the optimal system
performance. Impedance discontinuities at vias can be minimized or eliminated by increasing the swell around
each hole and providing for a low inductance return current path. When the via structure is associated with thick
backplane PCB, further optimization such as back drilling is often used to reduce the detrimental high frequency
effects of stubs on the signal path.
performance. Impedance discontinuities at vias can be minimized or eliminated by increasing the swell around
each hole and providing for a low inductance return current path. When the via structure is associated with thick
backplane PCB, further optimization such as back drilling is often used to reduce the detrimental high frequency
effects of stubs on the signal path.
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