Texas Instruments DS100BR111EVK Evaluation Module DS100BR111EVK/NOPB DS100BR111EVK/NOPB Datenbogen
Produktcode
DS100BR111EVK/NOPB
SNLS338E – JANUARY 2011 – REVISED FEBRUARY 2013
Power Supply Configuration Guidelines
The DS100BR111 can be configured for 2.5V operation or 3.3V operation. The lists below outline required
connections for each supply selection.
connections for each supply selection.
3.3V Mode of Operation
1. Tie VDD_SEL = 0 with 1K resistor to GND.
2. Feed 3.3V supply into VIN pin. Local 1.0 uF decoupling at VIN is recommended.
3. See information on VDD bypass below.
4. SDA and SCL pins should connect pull-up resistor to VIN
5. Any 4-Level input which requires a connection to "Logic 1" should use a 1K resistor to VIN
2.5V Mode of Operation
6. VDD_SEL = Float
7. VIN = Float
8. Feed 2.5V supply into VDD pins.
9. See information on VDD bypass below.
10. SDA and SCL pins connect pull-up resistor to VDD for 2.5V uC SMBus IO
11. SDA and SCL pins connect pull-up resistor to VDD for 3.3V uC SMBus IO
12. Any 4-Level input which requires a connection to "Logic 1" should use a 1K resistor to VIN
NOTE
The DAP (bottom solder pad) is the GND connection.
Power Supply Bypass
Two approaches are recommended to ensure that the DS100BR111 is provided with an adequate power supply.
First, the supply (VDD) and ground (GND) pins should be connected to power planes routed on adjacent layers
of the printed circuit board. The layer thickness of the dielectric should be minimized so that the V
First, the supply (VDD) and ground (GND) pins should be connected to power planes routed on adjacent layers
of the printed circuit board. The layer thickness of the dielectric should be minimized so that the V
DD
and GND
planes create a low inductance supply with distributed capacitance. Second, careful attention to supply
bypassing through the proper use of bypass capacitors is required. A 0.1
bypassing through the proper use of bypass capacitors is required. A 0.1
μ
F bypass capacitor should be
connected to each V
DD
pin such that the capacitor is placed as close as possible to the device. Smaller body size
capacitors can help facilitate proper component placement.
System Management Bus (SMBus) and Configuration Registers
The System Management Bus interface is compatible to SMBus 2.0 physical layer specification. ENSMB must be
pulled high to enable SMBus mode and allow access to the configuration registers.
pulled high to enable SMBus mode and allow access to the configuration registers.
The DS100BR111 has AD[3:0] inputs in SMBus mode. These pins are the user set SMBus slave address inputs.
When pulled low the AD[3:0] = 0000'b, the device default address byte is B0'h. Based on the SMBus 2.0
specification, this configuration results in a 7-bit slave address of 1011000'b. The LSB is set to 0'b (for a WRITE),
thus the 8-bit value is 1011 0000'b or B0'h. The device address byte can be set with the use of the AD[3:0]
inputs.
When pulled low the AD[3:0] = 0000'b, the device default address byte is B0'h. Based on the SMBus 2.0
specification, this configuration results in a 7-bit slave address of 1011000'b. The LSB is set to 0'b (for a WRITE),
thus the 8-bit value is 1011 0000'b or B0'h. The device address byte can be set with the use of the AD[3:0]
inputs.
Shown in the form of an expression:
Slave Address [7:4] = The DS100BR111 hardware address (1011'b) + Address pin AD[3]
Slave Address [3:1] = Address pins AD[2:0]
Slave Address [0] = 0'b for a WRITE or 1'b for a READ
Slave Address Examples:
•
AD[3:0] = 0001'b, the device slave address byte is B2'h
–
–
Slave Address [7:4] = 1011'b + 0'b = 1011'b or B'h
–
Slave Address [3:1] = 001'b
–
Slave Address [0] = 0'b for a WRITE
•
AD[3:0] = 0010'b, the device slave address byte is B4'h
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