Texas Instruments AM18x evaluation module with Wi-Fi TMDXEVMWIFI1808L TMDXEVMWIFI1808L Datenbogen

Produktcode
TMDXEVMWIFI1808L
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Peripheral 
Configuration
Bus
Noise
Filter
Noise
Filter
Clock Prescaler
I2CPSCx
Prescaler
Register
Bit Clock Generator
I2CCLKHx
Clock Divide
High Register
I2CCLKLx
Clock Divide
Low Register
Control
I2CCOARx
Own Address
Register
I2CSARx
Slave Address
Register
I2CCMDRx
Mode Register
I2CEMDRx
Extended Mode
Register
I2CCNTx
Data Count
Register
I2CPID1
Peripheral ID
Register 1
I2CPID2
Peripheral ID
Register 2
Transmit
I2CXSRx
Transmit Shift
Register
I2CDXRx
Transmit Buffer
Receive
I2CDRRx
Receive Buffer
I2CRSRx
Receive Shift
Register
I2Cx_SCL
I2Cx_SDA
Control
Interrupt/DMA
I2CIERx
Interrupt Enable
Register
I2CSTRx
Interrupt Status
Register
I2CSRCx
Interrupt Source
Register
Control
I2CPFUNC
Pin Function
Register
I2CPDIR
Pin Direction
Register
I2CPDIN
Pin Data In
Register
I2CPDOUT
Pin Data Out
Register
I2CPDSET
Pin Data Set
Register
I2CPDCLR
Pin Data Clear
Register
Interrupt DMA
Requests
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
6.18 Inter-Integrated Circuit Serial Ports (I2C)
6.18.1 I2C Device-Specific Information
Each I2C port supports:
Compatible with Philips® I2C Specification Revision 2.1 (January 2000)
Fast Mode up to 400 Kbps (no fail-safe I/O buffers)
Noise Filter to Remove Noise 50 ns or less
Seven- and Ten-Bit Device Addressing Modes
Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality
Events: DMA, Interrupt, or Polling
General-Purpose I/O Capability if not used as I2C
is block diagram of the device I2C Module.
Figure 6-40. I2C Module Block Diagram
172
Peripheral Information and Electrical Specifications
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