Benutzerhandbuch für Texas Instruments AM18x evaluation module with Wi-Fi TMDXEVMWIFI1808L

Inhaltsverzeichnis

• 1  AM1808 ARM Microprocessor

  1
  • 1.1 Features

    1
  • 1.2 Applications

    2
  • 1.3 Description

    3
  • 1.4 Functional Block Diagram

    4
• Table of Contents

  5
• 2 Revision History

  6
• 3 Device Overview

  7
  • 3.1 Device Characteristics

    7
  • 3.2 Device Compatibility

    8
  • 3.3 ARM Subsystem

    8
    • 3.3.1 ARM926EJ-S RISC CPU

      8
    • 3.3.2 CP15

      8
    • 3.3.3 MMU

      9
    • 3.3.4 Caches and Write Buffer

      9
    • 3.3.5 Advanced High-Performance Bus (AHB)

      9
    • 3.3.6 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)

      10
    • 3.3.7 ARM Memory Mapping

      10
  • 3.4 Memory Map Summary

    11
  • 3.5 Pin Assignments

    14
    • 3.5.1  Pin Map (Bottom View)

      14
  • 3.6 Pin Multiplexing Control

    17
  • 3.7 Terminal Functions

    18
    • 3.7.1  Device Reset and JTAG

      18
    • 3.7.2  High-Frequency Oscillator and PLL

      19
    • 3.7.3  Real-Time Clock and 32-kHz Oscillator

      20
    • 3.7.4  DEEPSLEEP Power Control

      20
    • 3.7.5  External Memory Interface A (EMIFA)

      21
    • 3.7.6  DDR2/mDDR Memory Controller

      24
    • 3.7.7  Serial Peripheral Interface Modules (SPI)

      26
    • 3.7.8  Programmable Real-Time Unit (PRU)

      27
    • 3.7.9 Enhanced Capture/Auxiliary PWM Modules (eCAP0)

      31
    • 3.7.10  Enhanced Pulse Width Modulators (eHRPWM)

      32
    • 3.7.11  Boot

      33
    • 3.7.12 Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)

      34
    • 3.7.13 Inter-Integrated Circuit Modules(I2C0, I2C1)

      35
    • 3.7.14 Timers

      36
    • 3.7.15 Multichannel Audio Serial Ports (McASP)

      37
    • 3.7.16 Multichannel Buffered Serial Ports (McBSP)

      38
    • 3.7.17 Universal Serial Bus Modules (USB0, USB1)

      39
    • 3.7.18 Ethernet Media Access Controller (EMAC)

      40
    • 3.7.19 Multimedia Card/Secure Digital (MMC/SD)

      42
    • 3.7.20  Liquid Crystal Display Controller(LCD)

      43
    • 3.7.21 Serial ATA Controller (SATA)

      44
    • 3.7.22  Universal Host-Port Interface (UHPI)

      45
    • 3.7.23  Universal Parallel Port (uPP)

      47
    • 3.7.24  Video Port Interface (VPIF)

      49
    • 3.7.25 General Purpose Input Output

      51
    • 3.7.26 Reserved and No Connect

      56
    • 3.7.27 Supply and Ground

      57
  • 3.8 Unused Pin Configurations

    58
• 4 Device Configuration

  60
  • 4.1 Boot Modes

    60
  • 4.2 SYSCFG Module

    60
  • 4.3 Pullup/Pulldown Resistors

    63
• 5 Specifications

  64
  • 5.1 Absolute Maximum Ratings Over Operating Junction Temperature Range (Unless Otherwise Noted)

    64
  • 5.2 Handling Ratings

    64
  • 5.3 Recommended Operating Conditions

    65
  • 5.4 Notes on Recommended Power-On Hours (POH)

    67
  • 5.5 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Junction Temperature (Unless Otherwise Noted)

    68
• 6 Peripheral Information and Electrical Specifications

  69
  • 6.1 Parameter Information

    69
    • 6.1.1 Parameter Information Device-Specific Information

      69
      • 6.1.1.1  Signal Transition Levels

        69
  • 6.2 Recommended Clock and Control Signal Transition Behavior

    70
  • 6.3 Power Supplies

    70
    • 6.3.1 Power-On Sequence

      70
    • 6.3.2 Power-Off Sequence

      70
  • 6.4 Reset

    71
    • 6.4.1 Power-On Reset (POR)

      71
    • 6.4.2 Warm Reset

      71
    • 6.4.3 Reset Electrical Data Timings

      73
  • 6.5 Crystal Oscillator or External Clock Input

    75
  • 6.6 Clock PLLs

    76
    • 6.6.1 PLL Device-Specific Information

      77
    • 6.6.2 Device Clock Generation

      79
    • 6.6.3 Dynamic Voltage and Frequency Scaling (DVFS)

      79
  • 6.7 Interrupts

    81
    • 6.7.1 ARM CPU Interrupts

      81
      • 6.7.1.1 ARM Interrupt Controller (AINTC) Interrupt Signal Hierarchy

        81
      • 6.7.1.2 AINTC Hardware Vector Generation

        81
      • 6.7.1.3 AINTC Hardware Interrupt Nesting Support

        81
      • 6.7.1.4 AINTC System Interrupt Assignments

        82
      • 6.7.1.5 AINTC Memory Map

        85
  • 6.8 Power and Sleep Controller (PSC)

    87
    • 6.8.1 Power Domain and Module Topology

      89
      • Module States

        91
  • 6.9 EDMA

    92
    • 6.9.1 EDMA3 Channel Synchronization Events

      92
    • 6.9.2 EDMA Peripheral Register Descriptions

      93
  • 6.10 External Memory Interface A (EMIFA)

    98
    • 6.10.1 EMIFA Asynchronous Memory Support

      98
    • 6.10.2 EMIFA Synchronous DRAM Memory Support

      98
    • 6.10.3 EMIFA SDRAM Loading Limitations

      99
    • 6.10.4 External Memory Interface Register Descriptions

      100
    • 6.10.5 EMIFA Electrical Data/Timing

      101
  • 6.11 DDR2/mDDR Memory Controller

    109
    • 6.11.1 DDR2/mDDR Memory Controller Electrical Data/Timing

      109
    • 6.11.2 DDR2/mDDR Controller Register Description(s)

      110
    • 6.11.3 DDR2/mDDR Interface

      110
      • 6.11.3.1 DDR2/mDDR Interface Schematic

        110
      • 6.11.3.2 Compatible JEDEC DDR2/mDDR Devices

        113
      • 6.11.3.3 PCB Stackup

        113
      • 6.11.3.4 Placement

        114
      • 6.11.3.5 DDR2/mDDR Keep Out Region

        115
      • 6.11.3.6 Bulk Bypass Capacitors

        116
      • 6.11.3.7 High-Speed Bypass Capacitors

        116
      • 6.11.3.8 Net Classes

        117
      • 6.11.3.9 DDR2/mDDR Signal Termination

        117
      • 6.11.3.10 VREF Routing

        118
      • 6.11.3.11 DDR2/mDDR CK and ADDR_CTRL Routing

        119
      • 6.11.3.12 MDDR/DDR2 Boundary Scan Limitations

        121
  • 6.12 Memory Protection Units

    122
  • 6.13 MMC / SD / SDIO (MMCSD0, MMCSD1)

    125
    • 6.13.1 MMCSD Peripheral Description

      125
    • 6.13.2  MMCSD Peripheral Register Description(s)

      125
    • 6.13.3 MMC/SD Electrical Data/Timing

      126
  • 6.14 Serial ATA Controller (SATA)

    128
    • 6.14.1 SATA Register Descriptions

      129
    • 6.14.2 SATA Interface

      130
      • 6.14.2.1 SATA Interface Schematic

        130
      • Compatible SATA Components and Modes

        130
      • 6.14.2.2 PCB Stackup Specifications

        131
      • 6.14.2.3 Routing Specifications

        131
      • 6.14.2.4 Coupling Capacitors

        131
      • 6.14.2.5 SATA Interface Clock Source requirements

        132
    • 6.14.3 SATA Unused Signal Configuration

      132
  • 6.15 Multichannel Audio Serial Port (McASP)

    133
    • 6.15.1 McASP Peripheral Registers Description(s)

      134
    • 6.15.2 McASP Electrical Data/Timing

      137
      • 6.15.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing

        137
  • 6.16 Multichannel Buffered Serial Port (McBSP)

    142
    • 6.16.1 McBSP Peripheral Register Description(s)

      142
    • 6.16.2 McBSP Electrical Data/Timing

      143
      • 6.16.2.1  Multichannel Buffered Serial Port (McBSP) Timing

        143
  • 6.17 Serial Peripheral Interface Ports (SPI0, SPI1)

    151
    • 6.17.1 SPI Peripheral Registers Description(s)

      153
    • 6.17.2 SPI Electrical Data/Timing

      154
      • 6.17.2.1 Serial Peripheral Interface (SPI) Timing

        154
  • 6.18 Inter-Integrated Circuit Serial Ports (I2C)

    172
    • 6.18.1 I2C Device-Specific Information

      172
    • 6.18.2 I2C Peripheral Registers Description(s)

      173
    • 6.18.3 I2C Electrical Data/Timing

      174
      • 6.18.3.1 Inter-Integrated Circuit (I2C) Timing

        174
  • 6.19 Universal Asynchronous Receiver/Transmitter (UART)

    176
    • 6.19.1 UART Peripheral Registers Description(s)

      176
    • 6.19.2 UART Electrical Data/Timing

      177
  • 6.20 Universal Serial Bus OTG Controller (USB0) [USB2.0 OTG]

    178
    • USB Peripheral Registers Description(s)

      178
    • 6.20.1 USB0 [USB2.0] Electrical Data/Timing

      184
  • 6.21 Universal Serial Bus Host Controller (USB1) [USB1.1 OHCI]

    185
  • 6.22 Ethernet Media Access Controller (EMAC)

    186
    • 6.22.1  EMAC Peripheral Register Description(s)

      186
    • 6.22.2 EMAC Electrical Data/Timing

      190
  • 6.23 Management Data Input/Output (MDIO)

    193
    • 6.23.1 MDIO Registers

      193
    • 6.23.2 Management Data Input/Output (MDIO) Electrical Data/Timing

      194
  • 6.24 LCD Controller (LCDC)

    195
    • 6.24.1 LCD Interface Display Driver (LIDD Mode)

      196
    • 6.24.2 LCD Raster Mode

      204
  • 6.25 Host-Port Interface (UHPI)

    210
    • 6.25.1 HPI Device-Specific Information

      210
    • 6.25.2 HPI Peripheral Register Description(s)

      210
    • 6.25.3 HPI Electrical Data/Timing

      211
  • 6.26 Universal Parallel Port (uPP)

    218
    • 6.26.1 uPP Register Descriptions

      219
    • 6.26.2 uPP Electrical Data/Timing

      220
  • 6.27 Video Port Interface (VPIF)

    223
    • 6.27.1 VPIF Register Descriptions

      223
    • 6.27.2 VPIF Electrical Data/Timing

      226
  • 6.28 Enhanced Capture (eCAP) Peripheral

    228
  • 6.29 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)

    231
    • 6.29.1 eHRPWM Register Descriptions

      232
    • 6.29.2 Enhanced Pulse Width Modulator (eHRPWM) Timing

      234
    • 6.29.3 Trip-Zone Input Timing

      235
  • 6.30 Timers

    236
    • 6.30.1 Timer Electrical Data/Timing

      237
  • 6.31 Real Time Clock (RTC)

    238
    • 6.31.1 Clock Source

      239
    • 6.31.2 Real-Time Clock Register Descriptions

      240
  • 6.32 General-Purpose Input/Output (GPIO)

    241
    • 6.32.1 GPIO Register Description(s)

      242
    • 6.32.2  GPIO Peripheral Input/Output Electrical Data/Timing

      244
    • 6.32.3  GPIO Peripheral External Interrupts Electrical Data/Timing

      244
  • 6.33 Programmable Real-Time Unit Subsystem (PRUSS)

    245
    • 6.33.1 PRUSS Register Descriptions

      246
  • 6.34 Emulation Logic

    248
    • 6.34.1 JTAG Port Description

      249
    • 6.34.2 Scan Chain Configuration Parameters

      250
    • 6.34.3 Initial Scan Chain Configuration

      250
      • 6.34.3.1 Adding TAPS to the Scan Chain

        250
    • 6.34.4 IEEE 1149.1 JTAG

      254
      • 6.34.4.1  JTAG Peripheral Register Description(s) – JTAG ID Register (DEVIDR0)

        254
      • 6.34.4.2  JTAG Test-Port Electrical Data/Timing

        255
    • 6.34.5 JTAG 1149.1 Boundary Scan Considerations

      255
• 7 Device and Documentation Support

  256
  • 7.1 Device Support

    256
    • 7.1.1 Development Support

      256
    • 7.1.2 Device and Development-Support Tool Nomenclature

      256
  • 7.2 Documentation Support

    257
  • 7.3 Community Resources

    257
  • 7.4 Trademarks

    257
  • 7.5 Electrostatic Discharge Caution

    258
  • 7.6 Glossary

    258
• 8 Mechanical Packaging and Orderable Information

  258
  • 8.1 Thermal Data for ZCE Package

    258
  • 8.2 Thermal Data for ZWT Package

    259