Texas Instruments AM18x evaluation module with Wi-Fi TMDXEVMWIFI1808L TMDXEVMWIFI1808L Datenbogen
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TMDXEVMWIFI1808L
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
6.19 Universal Asynchronous Receiver/Transmitter (UART)
Each UART has the following features:
•
16-byte storage space for both the transmitter and receiver FIFOs
•
1, 4, 8, or 14 byte selectable receiver FIFO trigger level for autoflow control and DMA
•
DMA signaling capability for both received and transmitted data
•
Programmable auto-rts and auto-cts for autoflow control
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Programmable Baud Rate up to 12 MBaud
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Programmable Oversampling Options of x13 and x16
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Frequency pre-scale values from 1 to 65,535 to generate appropriate baud rates
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Prioritized interrupts
•
Programmable serial data formats
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–
5, 6, 7, or 8-bit characters
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Even, odd, or no parity bit generation and detection
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1, 1.5, or 2 stop bit generation
•
False start bit detection
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Line break generation and detection
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Internal diagnostic capabilities
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Loopback controls for communications link fault isolation
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Break, parity, overrun, and framing error simulation
•
Modem control functions (CTS, RTS)
The UART registers are listed in
6.19.1 UART Peripheral Registers Description(s)
is the list of UART registers.
Table 6-83. UART Registers
UART0
UART1
UART2
ACRONYM
REGISTER DESCRIPTION
BYTE ADDRESS
BYTE ADDRESS
BYTE ADDRESS
0x01C4 2000
0x01D0 C000
0x01D0 D000
RBR
Receiver Buffer Register (read only)
0x01C4 2000
0x01D0 C000
0x01D0 D000
THR
Transmitter Holding Register (write only)
0x01C4 2004
0x01D0 C004
0x01D0 D004
IER
Interrupt Enable Register
0x01C4 2008
0x01D0 C008
0x01D0 D008
IIR
Interrupt Identification Register (read only)
0x01C4 2008
0x01D0 C008
0x01D0 D008
FCR
FIFO Control Register (write only)
0x01C4 200C
0x01D0 C00C
0x01D0 D00C
LCR
Line Control Register
0x01C4 2010
0x01D0 C010
0x01D0 D010
MCR
Modem Control Register
0x01C4 2014
0x01D0 C014
0x01D0 D014
LSR
Line Status Register
0x01C4 2018
0x01D0 C018
0x01D0 D018
MSR
Modem Status Register
0x01C4 201C
0x01D0 C01C
0x01D0 D01C
SCR
Scratchpad Register
0x01C4 2020
0x01D0 C020
0x01D0 D020
DLL
Divisor LSB Latch
0x01C4 2024
0x01D0 C024
0x01D0 D024
DLH
Divisor MSB Latch
0x01C4 2028
0x01D0 C028
0x01D0 D028
REVID1
Revision Identification Register 1
0x01C4 2030
0x01D0 C030
0x01D0 D030
PWREMU_MGMT
Power and Emulation Management Register
0x01C4 2034
0x01D0 C034
0x01D0 D034
MDR
Mode Definition Register
176
Peripheral Information and Electrical Specifications
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