Texas Instruments AM18x evaluation module with Wi-Fi TMDXEVMWIFI1808L TMDXEVMWIFI1808L Datenbogen
Produktcode
TMDXEVMWIFI1808L
VP_CLKIN0/1
VP_DINx/FIELD/
HSYNC/VSYNC
1
2
VP_CLKINx
2
3
1
4
4
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
6.27.2 VPIF Electrical Data/Timing
Table 6-115. Timing Requirements for VPIF VP_CLKINx Inputs
(1)
(see
1.3V, 1.2V
1.1V
1.0V
NO.
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
Cycle time, VP_CLKIN0
13.3
20
37
ns
1
t
c(VKI)
Cycle time, VP_CLKIN1/2/3
13.3
20
37
ns
2
t
w(VKIH)
Pulse duration, VP_CLKINx high
0.4C
0.4C
0.4C
ns
3
t
w(VKIL)
Pulse duration, VP_CLKINx low
0.4C
0.4C
0.4C
ns
4
t
t(VKI)
Transition time, VP_CLKINx
5
5
5
ns
(1)
C = VP_CLKINx period in ns.
Figure 6-73. Video Port Capture VP_CLKINx Timing
Table 6-116. Timing Requirements for VPIF Channels 0/1 Video Capture Data and Control Inputs
(see
)
1.3V
1.2V
1.1V
1.0V
NO.
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Setup time, VP_DINx valid before
1
t
su(VDINV-VKIH)
4
4
6
7
ns
VP_CLKIN0/1 high
Hold time, VP_DINx valid after
2
t
h(VKIH-VDINV)
0.5
0
0
0
ns
VP_CLKIN0/1 high
Figure 6-74. VPIF Channels 0/1 Video Capture Data and Control Input Timing
226
Peripheral Information and Electrical Specifications
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