Texas Instruments DRV8802 Evaluation Module DRV8802EVM DRV8802EVM Datenbogen
Produktcode
DRV8802EVM
SLVSAM9C – APRIL 2011 – REVISED AUGUST 2013
THERMAL INFORMATION
DRV8802
THERMAL METRIC
(1)
PWP
UNITS
28 PINS
θ
JA
Junction-to-ambient thermal resistance
(2)
38.9
θ
JCtop
Junction-to-case (top) thermal resistance
(3)
23.3
θ
JB
Junction-to-board thermal resistance
(4)
21.2
°C/W
ψ
JT
Junction-to-top characterization parameter
(5)
0.8
ψ
JB
Junction-to-board characterization parameter
(6)
20.9
θ
JCbot
Junction-to-case (bottom) thermal resistance
(7)
2.6
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report,
(2)
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
specified in JESD51-7, in an environment described in JESD51-2a.
(3)
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4)
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
temperature, as described in JESD51-8.
(5)
The junction-to-top characterization parameter,
ψ
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6)
The junction-to-board characterization parameter,
ψ
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(7)
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
V
M
Motor power supply voltage range
(1)
8.2
45
V
V
REF
VREF input voltage
(2)
1
3.5
V
I
V3P3
V3P3OUT load current
1
mA
(1)
All V
M
pins must be connected to the same supply voltage.
(2)
Operational at VREF between 0 V and 1 V, but accuracy is degraded.
Copyright © 2011–2013, Texas Instruments Incorporated
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