Microchip Technology DM183037 Datenbogen
PIC18F97J94 FAMILY
DS30575A-page 688
2012 Microchip Technology Inc.
CLKO and I/O .......................................................... 644
Clock Jitter Causing Pulse Between Consecutive
Clock Jitter Causing Pulse Between Consecutive
Clock Synchronization ............................................. 391
Clock Transition ......................................................... 58
Clock/Instruction Cycle ...................................... 38, 118
Converting 1 Channel 16 Times per Interrupt .......... 477
Converting 1 Channel, Auto-Sample Start, Manual
Clock Transition ......................................................... 58
Clock/Instruction Cycle ...................................... 38, 118
Converting 1 Channel 16 Times per Interrupt .......... 477
Converting 1 Channel, Auto-Sample Start, Manual
Converting 1 Channel, Auto-Sample Start, T
AD
Converting 1 Channel, Manual Sample Start,
T
AD
Example SPI Master Mode (CKE = 0) ..................... 651
Example SPI Master Mode (CKE = 1) ..................... 652
Example SPI Slave Mode (CKE = 0) ....................... 653
Example SPI Slave Mode (CKE = 1) ....................... 654
External Clock .......................................................... 642
External Memory Bus for SLEEP (Extended
Example SPI Master Mode (CKE = 1) ..................... 652
Example SPI Slave Mode (CKE = 0) ....................... 653
Example SPI Slave Mode (CKE = 1) ....................... 654
External Clock .......................................................... 642
External Memory Bus for SLEEP (Extended
Fail-Safe Clock Monitor (FSCM) .............................. 572
First Start Bit Timing ................................................ 399
Full-Bridge PWM Output .......................................... 328
Half-Bridge PWM Output ................................. 326, 333
High-Voltage Detect Operation (VDIRMAG = 1) ...... 504
HLVD Characteristics ............................................... 648
I
First Start Bit Timing ................................................ 399
Full-Bridge PWM Output .......................................... 328
Half-Bridge PWM Output ................................. 326, 333
High-Voltage Detect Operation (VDIRMAG = 1) ...... 504
HLVD Characteristics ............................................... 648
I
2
I
2
I
2
I
2
I
2
I
2
I
2
I
2
I
2
I
2
I
2
I
2
I
2
I
2
I
2
Inverted IrDA Encoding (TXCKP = 1) ...................... 432
Inverted Polarity Decoding Results (RXDTP = 1) .... 433
Inverted Polarity Decoding Results (RXDTP = 1) .... 433
IrDA Encoding Scheme ........................................... 432
LCD Reference Ladder Power Mode Switching ...... 254
LCD Sleep Entry/Exit When SLPEN = 1 or
LCD Reference Ladder Power Mode Switching ...... 254
LCD Sleep Entry/Exit When SLPEN = 1 or
MSSPx I
2
MSSPx I
2
Parallel Slave Port (PSP) Read ............................... 223
Parallel Slave Port (PSP) Write ............................... 222
POR Module for Rising V
Parallel Slave Port (PSP) Write ............................... 222
POR Module for Rising V
DD
Program Memory Fetch (8-bit) ................................. 645
Program Memory Read ........................................... 646
PWM Auto-Shutdown with Auto-Restart Enabled
Program Memory Read ........................................... 646
PWM Auto-Shutdown with Auto-Restart Enabled
PWM Direction Change ........................................... 329
PWM Direction Change at Near 100% Duty Cycle .. 330
PWM Output ............................................................ 348
PWM Output (Active-High) ...................................... 324
PWM Output (Active-Low) ....................................... 325
Repeated Start Condition ........................................ 400
Reset, Watchdog Timer (WDT), Oscillator Start-up
PWM Direction Change at Near 100% Duty Cycle .. 330
PWM Output ............................................................ 348
PWM Output (Active-High) ...................................... 324
PWM Output (Active-Low) ....................................... 325
Repeated Start Condition ........................................ 400
Reset, Watchdog Timer (WDT), Oscillator Start-up
Scanning All 16 Inputs per Single Interrupt ............. 479
Send Break Character Sequence ............................ 426
Slave Synchronization ............................................. 359
SPI Mode (Master Mode) ......................................... 358
SPI Mode (Slave Mode, CKE = 0) ........................... 360
SPI Mode (Slave Mode, CKE = 1) ........................... 360
Steering Event at Beginning of Instruction
Send Break Character Sequence ............................ 426
Slave Synchronization ............................................. 359
SPI Mode (Master Mode) ......................................... 358
SPI Mode (Slave Mode, CKE = 0) ........................... 360
SPI Mode (Slave Mode, CKE = 1) ........................... 360
Steering Event at Beginning of Instruction
Synchronous Reception (Master Mode, SREN) ...... 429
Synchronous Transmission ..................................... 428
Synchronous Transmission (Through TXEN) .......... 428
Timer Pulse Generation ........................................... 315
Timer0 and Timer1 External Clock .......................... 649
Timer1/3/5 Gate Count Enable Mode ...................... 289
Timer1/3/5 Gate Single Pulse Mode ........................ 291
Timer1/3/5 Gate Single Pulse/Toggle Combined
Synchronous Transmission ..................................... 428
Synchronous Transmission (Through TXEN) .......... 428
Timer Pulse Generation ........................................... 315
Timer0 and Timer1 External Clock .......................... 649
Timer1/3/5 Gate Count Enable Mode ...................... 289
Timer1/3/5 Gate Single Pulse Mode ........................ 291
Timer1/3/5 Gate Single Pulse/Toggle Combined
Timing Diagrams and Specifications