Microchip Technology DM183037 Datenbogen
2012 Microchip Technology Inc.
DS30575A-page 689
PIC18F97J94 FAMILY
Example SPI Slave Mode Requirements (CKE = 1) 654
External Clock Requirements .................................. 642
HLVD Characteristics ............................................... 648
I
External Clock Requirements .................................. 642
HLVD Characteristics ............................................... 648
I
2
I
2
MSSPx I
PLL Clock ................................................................. 643
Program Memory Fetch Requirements (8-Bit) ......... 645
Reset, Watchdog Timer, Oscillator Start-up Timer,
Program Memory Fetch Requirements (8-Bit) ......... 645
Reset, Watchdog Timer, Oscillator Start-up Timer,
Top-of-Stack Access ........................................................ 115
TSTFSZ ........................................................................... 615
Two-Speed Start-up ........................................... 62, 553, 570
TSTFSZ ........................................................................... 615
Two-Speed Start-up ........................................... 62, 553, 570
Two-Word Instructions
TXSTAx Register
U
Address Register (UADDR) ..................................... 533
Associated Registers ............................................... 549
Buffer Descriptor Table ............................................ 534
Buffer Descriptors .................................................... 534
Associated Registers ............................................... 549
Buffer Descriptor Table ............................................ 534
Buffer Descriptors .................................................... 534
Address Validation ........................................... 537
Assignment in Different Buffering Modes ........ 539
BDnSTAT Register (CPU Mode) ..................... 535
BDnSTAT Register (SIE Mode) ....................... 537
Byte Count ....................................................... 537
Memory Map .................................................... 538
Ownership ........................................................ 534
Ping-Pong Buffering ......................................... 538
Register Summary ........................................... 539
Status and Configuration ................................. 534
Assignment in Different Buffering Modes ........ 539
BDnSTAT Register (CPU Mode) ..................... 535
BDnSTAT Register (SIE Mode) ....................... 537
Byte Count ....................................................... 537
Memory Map .................................................... 538
Ownership ........................................................ 534
Ping-Pong Buffering ......................................... 538
Register Summary ........................................... 539
Status and Configuration ................................. 534
Endpoint Control ...................................................... 532
External Pull-up Resistors ........................................ 530
Eye Pattern Test Enable .......................................... 530
Firmware and Drivers ............................................... 549
Frame Number Registers ......................................... 533
Internal Pull-up Resistors ......................................... 530
Internal Transceiver ................................................. 528
Interrupts .................................................................. 540
External Pull-up Resistors ........................................ 530
Eye Pattern Test Enable .......................................... 530
Firmware and Drivers ............................................... 549
Frame Number Registers ......................................... 533
Internal Pull-up Resistors ......................................... 530
Internal Transceiver ................................................. 528
Interrupts .................................................................. 540
Oscillator Requirements ........................................... 549
Overview .......................................................... 525, 550
Overview .......................................................... 525, 550
Class Specifications and Drivers ..................... 551
Descriptors ....................................................... 551
Enumeration .................................................... 551
Frames ............................................................. 550
Layered Framework ......................................... 550
Power ............................................................... 550
Speed .............................................................. 551
Transfer Types ................................................. 550
Descriptors ....................................................... 551
Enumeration .................................................... 551
Frames ............................................................. 550
Layered Framework ......................................... 550
Power ............................................................... 550
Speed .............................................................. 551
Transfer Types ................................................. 550
Ping-Pong Buffer Configuration ............................... 530
Power Modes ........................................................... 546
Power Modes ........................................................... 546
Bus Power Only ............................................... 546
Dual Power with Self-Power Dominance ......... 546
Self-Power Only ............................................... 546
Transceiver Current Consumption ................... 547
Dual Power with Self-Power Dominance ......... 546
Self-Power Only ............................................... 546
Transceiver Current Consumption ................... 547
Status and Control ................................................... 526
UFRMH:UFRML Registers ...................................... 533
UFRMH:UFRML Registers ...................................... 533
USB
USB. See Universal Serial Bus.
V
W
Control Register ....................................................... 569
During Oscillator Failure .......................................... 571
Programming Considerations .................................. 568
During Oscillator Failure .......................................... 571
Programming Considerations .................................. 568
WCOL ...................................................... 399, 400, 401, 404
WCOL Status Flag ................................... 399, 400, 401, 404
WWW Address ................................................................ 691
WWW, On-Line Support ...................................................... 7
WCOL Status Flag ................................... 399, 400, 401, 404
WWW Address ................................................................ 691
WWW, On-Line Support ...................................................... 7
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