Texas Instruments Hercules TMS570LS04x/03x LaunchPad Evaluation Kit LAUNCHXL-TMS57004 LAUNCHXL-TMS57004 Datenbogen
Produktcode
LAUNCHXL-TMS57004
SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013
5.7.4
MibSPI/SPI Master Mode I/O Timing Specifications
Table 5-13. SPI Master Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO
= output, and SPISOMI = input)
(1) (2) (3)
NO.
Parameter
MIN
MAX
Unit
1
t
c(SPC)M
Cycle time, SPICLK
(4)
40
256t
c(VCLK)
ns
2
(5)
t
w(SPCH)M
Pulse duration, SPICLK high (clock
0.5t
c(SPC)M
– t
r(SPC)M
– 3
0.5t
c(SPC)M
+ 3
ns
polarity = 0)
t
w(SPCL)M
Pulse duration, SPICLK low (clock
0.5t
c(SPC)M
– t
f(SPC)M
– 3
0.5t
c(SPC)M
+ 3
polarity = 1)
3
(5)
t
w(SPCL)M
Pulse duration, SPICLK low (clock
0.5t
c(SPC)M
– t
f(SPC)M
– 3
0.5t
c(SPC)M
+ 3
ns
polarity = 0)
t
w(SPCH)M
Pulse duration, SPICLK high (clock
0.5t
c(SPC)M
– t
r(SPC)M
– 3
0.5t
c(SPC)M
+ 3
polarity = 1)
4
(5)
t
d(SPCH-SIMO)M
Delay time, SPISIMO valid before
0.5t
c(SPC)M
– 6
ns
SPICLK low (clock polarity = 0)
t
d(SPCL-SIMO)M
Delay time, SPISIMO valid before
0.5t
c(SPC)M
– 6
SPICLK high (clock polarity = 1)
5
(5)
t
v(SPCL-SIMO)M
Valid time, SPISIMO data valid after
0.5t
c(SPC)M
– t
f(SPC)
– 4
ns
SPICLK low (clock polarity = 0)
t
v(SPCH-SIMO)M
Valid time, SPISIMO data valid after
0.5t
c(SPC)M
– t
r(SPC)
– 4
SPICLK high (clock polarity = 1)
6
(5)
t
su(SOMI-SPCL)M
Setup time, SPISOMI before SPICLK
t
f(SPC)
+ 2.2
ns
low (clock polarity = 0)
t
su(SOMI-SPCH)M
Setup time, SPISOMI before SPICLK
t
r(SPC)
+ 2.2
high (clock polarity = 1)
7
(5)
t
h(SPCL-SOMI)M
Hold time, SPISOMI data valid after
10
ns
SPICLK low (clock polarity = 0)
t
h(SPCH-SOMI)M
Hold time, SPISOMI data valid after
10
SPICLK high (clock polarity = 1)
8
(6)
t
C2TDELAY
Setup time CS active
CSHOLD = 0
C2TDELAY*t
c(VCLK)
+ 2*t
c(VCLK)
(C2TDELAY+2) * t
c(VCLK)
-
ns
until SPICLK high
- t
f(SPICS)
+ t
r(SPC)
– 7
t
f(SPICS)
+ t
r(SPC)
+ 5.5
(clock polarity = 0)
CSHOLD = 1
C2TDELAY*t
c(VCLK)
+ 3*t
c(VCLK)
(C2TDELAY+3) * t
c(VCLK)
-
- t
f(SPICS)
+ t
r(SPC)
– 7
t
f(SPICS)
+ t
r(SPC)
+ 5.5
Setup time CS active
CSHOLD = 0
C2TDELAY*t
c(VCLK)
+ 2*t
c(VCLK)
(C2TDELAY+2) * t
c(VCLK)
-
ns
until SPICLK low
- t
f(SPICS)
+ t
f(SPC)
– 7
t
f(SPICS)
+ t
f(SPC)
+ 5.5
(clock polarity = 1)
CSHOLD = 1
C2TDELAY*t
c(VCLK)
+ 3*t
c(VCLK)
(C2TDELAY+3) * t
c(VCLK)
-
- t
f(SPICS)
+ t
f(SPC)
– 7
t
f(SPICS)
+ t
f(SPC)
+ 5.5
9
(6)
t
T2CDELAY
Hold time SPICLK low until CS inactive
0.5*t
c(SPC)M
+
0.5*t
c(SPC)M
+
ns
(clock polarity = 0)
T2CDELAY*t
c(VCLK)
+ t
c(VCLK)
-
T2CDELAY*t
c(VCLK)
+ t
c(VCLK)
-
t
f(SPC)
+ t
r(SPICS)
- 7
t
f(SPC)
+ t
r(SPICS)
+ 11
Hold time SPICLK high until CS
0.5*t
c(SPC)M
+
0.5*t
c(SPC)M
+
ns
inactive (clock polarity = 1)
T2CDELAY*t
c(VCLK)
+ t
c(VCLK)
-
T2CDELAY*t
c(VCLK)
+ t
c(VCLK)
-
t
r(SPC)
+ tr(SPICS) - 7
t
r(SPC)
+ t
r(SPICS)
+ 11
10
t
SPIENA
SPIENAn Sample point
(C2TDELAY+1) * t
c(VCLK)
-
(C2TDELAY+1)*t
c(VCLK)
ns
t
f(SPICS)
– 29
11
t
SPIENAW
SPIENAn Sample point from write to
(C2TDELAY+2)*t
c(VCLK)
ns
buffer
(1)
The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is cleared.
(2)
t
c(VCLK)
= interface clock cycle time = 1 / f
(VCLK)
(3)
For rise and fall timings, see
(4)
When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255: t
For PS values from 1 to 255: t
c(SPC)M
≥ (PS +1)t
c(VCLK)
≥ 40 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: t
c(SPC)M
= 2t
c(VCLK)
≥ 40 ns.
The external load on the SPICLK pin must be less than 60pF.
(5)
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(6)
C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
84
Peripheral Information and Electrical Specifications
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