Texas Instruments Hercules TMS570LS04x/03x LaunchPad Evaluation Kit LAUNCHXL-TMS57004 LAUNCHXL-TMS57004 Datenbogen
Produktcode
LAUNCHXL-TMS57004
SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013
Table 5-14. SPI Master Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO
= output, and SPISOMI = input)
(1) (2) (3)
NO.
Parameter
MIN
MAX
Unit
1
t
c(SPC)M
Cycle time, SPICLK
(4)
40
256t
c(VCLK)
ns
2
(5)
t
w(SPCH)M
Pulse duration, SPICLK high (clock
0.5t
c(SPC)M
– t
r(SPC)M
– 3
0.5t
c(SPC)M
+ 3
ns
polarity = 0)
t
w(SPCL)M
Pulse duration, SPICLK low (clock
0.5t
c(SPC)M
– t
f(SPC)M
– 3
0.5t
c(SPC)M
+ 3
polarity = 1)
3
(5)
t
w(SPCL)M
Pulse duration, SPICLK low (clock
0.5t
c(SPC)M
– t
f(SPC)M
– 3
0.5t
c(SPC)M
+ 3
ns
polarity = 0)
t
w(SPCH)M
Pulse duration, SPICLK high (clock
0.5t
c(SPC)M
– t
r(SPC)M
– 3
0.5t
c(SPC)M
+ 3
polarity = 1)
4
(5)
t
v(SIMO-SPCH)M
Valid time, SPICLK high after
0.5t
c(SPC)M
– 6
ns
SPISIMO data valid (clock polarity =
0)
0)
t
v(SIMO-SPCL)M
Valid time, SPICLK low after
0.5t
c(SPC)M
– 6
SPISIMO data valid (clock polarity =
1)
1)
5
(5)
t
v(SPCH-SIMO)M
Valid time, SPISIMO data valid after
0.5t
c(SPC)M
– t
r(SPC)
– 4
ns
SPICLK high (clock polarity = 0)
t
v(SPCL-SIMO)M
Valid time, SPISIMO data valid after
0.5t
c(SPC)M
– t
f(SPC)
– 4
SPICLK low (clock polarity = 1)
6
(5)
t
su(SOMI-SPCH)M
Setup time, SPISOMI before
t
r(SPC)
+ 2.2
ns
SPICLK high (clock polarity = 0)
t
su(SOMI-SPCL)M
Setup time, SPISOMI before
t
f(SPC)
+ 2.2
SPICLK low (clock polarity = 1)
7
(5)
t
v(SPCH-SOMI)M
Valid time, SPISOMI data valid after
10
ns
SPICLK high (clock polarity = 0)
t
v(SPCL-SOMI)M
Valid time, SPISOMI data valid after
10
SPICLK low (clock polarity = 1)
8
(6)
t
C2TDELAY
Setup time CS
CSHOLD = 0
0.5*t
c(SPC)M
+
0.5*t
c(SPC)M
+
ns
active until SPICLK
(C2TDELAY+2) * t
c(VCLK)
-
(C2TDELAY+2) * t
c(VCLK)
-
high (clock polarity =
t
f(SPICS)
+ t
r(SPC)
– 7
t
f(SPICS)
+ t
r(SPC)
+ 5.5
0)
CSHOLD = 1
0.5*t
c(SPC)M
+
0.5*t
c(SPC)M
+
(C2TDELAY+3) * t
c(VCLK)
-
(C2TDELAY+3) * t
c(VCLK)
-
t
f(SPICS)
+ t
r(SPC)
– 7
t
f(SPICS)
+ t
r(SPC)
+ 5.5
Setup time CS
CSHOLD = 0
0.5*t
c(SPC)M
+
0.5*t
c(SPC)M
+
ns
active until SPICLK
(C2TDELAY+2) * t
c(VCLK)
-
(C2TDELAY+2) * t
c(VCLK)
-
low (clock polarity =
t
f(SPICS)
+ t
f(SPC)
– 7
t
f(SPICS)
+ t
f(SPC)
+ 5.5
1)
CSHOLD = 1
0.5*t
c(SPC)M
+
0.5*t
c(SPC)M
+
(C2TDELAY+3) * t
c(VCLK)
-
(C2TDELAY+3) * t
c(VCLK)
-
t
f(SPICS)
+ t
f(SPC)
– 7
t
f(SPICS)
+ t
f(SPC)
+ 5.5
9
(6)
t
T2CDELAY
Hold time SPICLK low until CS
T2CDELAY*t
c(VCLK)
+
T2CDELAY*t
c(VCLK)
+
ns
inactive (clock polarity = 0)
t
c(VCLK)
- t
f(SPC)
+ t
r(SPICS)
-
t
c(VCLK)
- t
f(SPC)
+ t
r(SPICS)
+
7
11
Hold time SPICLK high until CS
T2CDELAY*t
c(VCLK)
+
T2CDELAY*t
c(VCLK)
+
ns
inactive (clock polarity = 1)
t
c(VCLK)
- t
r(SPC)
+ t
r(SPICS)
-
t
c(VCLK)
- t
r(SPC)
+ t
r(SPICS)
+
7
11
10
t
SPIENA
SPIENAn Sample Point
(C2TDELAY+1)* t
c(VCLK)
-
(C2TDELAY+1)*t
c(VCLK)
ns
t
f(SPICS)
– 29
11
t
SPIENAW
SPIENAn Sample point from write to
(C2TDELAY+2)*t
c(VCLK)
ns
buffer
(1)
The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.
(2)
t
c(VCLK)
= interface clock cycle time = 1 / f
(VCLK)
(3)
For rise and fall timings, see the
.
(4)
When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255: t
For PS values from 1 to 255: t
c(SPC)M
≥ (PS +1)t
c(VCLK)
≥ 40 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: t
c(SPC)M
= 2t
c(VCLK)
≥ 40 ns.
The external load on the SPICLK pin must be less than 60pF.
(5)
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(6)
C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
86
Peripheral Information and Electrical Specifications
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