Freescale Semiconductor KIT912F634EVME Evaluation Kit KIT912F634EVME KIT912F634EVME Datenbogen
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KIT912F634EVME
Functional Description and Application Information
Port Integration Module (9S12I32PIMV1)
MM912F634
Freescale Semiconductor
166
4.27
Port Integration Module (9S12I32PIMV1)
4.27.1
Introduction
The Port Integration Module (PIM) establishes the interface between the S12I32 peripheral modules SPI and the Die-To-Die
Interface module (D2DI) to the I/O pins of the MCU. Depending on the package option the D2DI related pins may or may not be
available externally; if used in a dual-die package this interface is internal.
Interface module (D2DI) to the I/O pins of the MCU. Depending on the package option the D2DI related pins may or may not be
available externally; if used in a dual-die package this interface is internal.
All pins support general purpose I/O functionality if not in use by the peripheral module. The PIM controls the signal prioritization
and multiplexing on the shared pins and the pull-down functionality on specific pins.
and multiplexing on the shared pins and the pull-down functionality on specific pins.
4.27.2
Features
•
6-pin port A associated with the SPI module
•
2-pin port C used as D2DI clock output and D2DI interrupt input
•
8-pin port D used as 8 or 4-bit data I/O for the D2DI interface
•
GPIO function shared on all pins
•
Pull-down devices on PC1 and PD7-0 if used as D2DI inputs
•
Reduced drive capability on port A on per pin basis
The Port Integration Module includes these distinctive registers:
•
Data registers for ports A, C, and D, when used as general-purpose I/O
•
Data direction registers for ports A, C, and D, when used as general-purpose I/O
•
Port input register on port A
•
Reduced drive register on port A
A standard port A pin has the following features:
•
Input/output selection
•
5.0 V output drive
•
5.0 V digital input
A standard port C and D pin has the following features:
•
Input/output selection
•
2.5 V output drive
•
2.5 V digital input
4.27.3
Memory Map
Table 216. Memory Map
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x0000
PTA
R
0
0
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
W
0x0001
Reserved
R
0
0
0
0
0
0
0
0
W
0x0002
DDRA
R
0
0
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
W
0x0003
Reserved
R
0
0
0
0
0
0
0
0
W
0x0004
PTC
R
0
0
0
0
0
0
PTC1
PTC0
W
0x0005
PTD
R
PTD7
PTD6
PTD5
PTD4
PTD3
PTD2
PTD1
PTD0
W