Datenbogen (KIT912F634EVME)InhaltsverzeichnisIntegrated S12 Based Relay Driver with LIN11 Ordering Information2Table of Contents32 Pin Assignment52.1 MM912F634 Pin Description62.2 MCU Die Signal Properties103 Electrical Characteristics113.1 General113.2 Absolute Maximum Ratings113.3 Operating Conditions133.4 Supply Currents133.4.1 Measurement Conditions133.5 Static Electrical Characteristics143.5.1 Static Electrical Characteristics Analog Die143.5.2 Static Electrical Characteristics MCU Die213.5.2.1 I/O Characteristics213.6 Dynamic Electrical Characteristics223.6.1 Dynamic Electrical Characteristics Analog Die223.6.2 Dynamic Electrical Characteristics MCU Die263.6.2.1 NVM Timing263.6.2.1.1 Single Word Programming263.6.2.1.2 Burst Programming273.6.2.1.3 Sector Erase273.6.2.1.4 Mass Erase273.6.2.1.5 Blank Check283.6.2.2 NVM Reliability293.6.2.3 Reset, Oscillator and Internal Clock Generation303.6.2.3.1 Startup & FLL Characteristics303.6.2.3.2 Power On Reset313.6.2.3.3 Oscillator323.6.2.4 SPI Timing323.6.2.4.1 Master Mode333.6.2.4.2 Slave Mode353.7 Thermal Protection Characteristics373.8 ESD Protection and Latch-up Immunity383.9 Additional Test Information ISO7637-2394 Functional Description and Application Information404.1 Introduction404.1.1 Device Register Maps404.1.2 Detailed Module Register Maps414.2 MM912F634 - Analog Die Overview524.2.1 Introduction524.2.2 System Registers524.2.2.1 Silicon Revision Register (SRR)524.2.3 Analog Die Options524.2.3.1 Current Sense Module534.2.3.1.1 Pinout considerations534.2.3.1.2 Register Considerations534.2.3.1.3 Functional Considerations544.2.3.2 Wake-up Inputs (Lx)544.2.3.2.1 Pinout Considerations544.2.3.2.2 Register Considerations544.2.3.2.3 Functional Considerations554.3 Modes of Operation564.3.1 Power Down Mode564.3.2 Reset Mode564.3.3 Normal Mode574.3.4 Stop Mode574.3.5 Sleep Mode584.3.6 Analog Die Functionality by Operation Mode584.3.7 Register Definition594.3.7.1 Mode Control Register (MCR)594.4 Power Supply604.4.1 Voltage Regulators VDD (2.5 V) & VDDX (5.0 V)614.4.2 Power Up Behavior / Power Down Behavior614.4.3 Power Up Behavior / Power Down Behavior - I64634.4.4 Register Definition644.4.4.1 Voltage Control Register (VCR)644.4.4.2 Voltage Status Register (VSR)654.5 Die to Die Interface - Target664.5.1 Overview664.5.2 Low Power Mode Operation664.5.2.1 Normal Mode / Stop Mode664.5.2.2 Sleep Mode664.6 Interrupts674.6.1 Interrupt Source Identification674.6.1.1 Interrupt Source Mirror674.6.1.1.1 Interrupt Source Register (ISR)674.6.1.2 Interrupt Vector Emulation by Priority684.6.1.2.1 Interrupt Vector Register (IVR)684.6.2 Interrupt Sources694.6.2.1 Voltage Status Interrupt (VSI)694.6.2.2 Low Voltage Interrupt (LVI)694.6.2.3 Voltage Regulator High Temperature Interrupt (HTI)694.6.2.4 Low Battery Interrupt (LBI)694.6.2.5 TIM Channel 0 Interrupt (CH0)694.6.2.6 TIM Channel 1 Interrupt (CH1)704.6.2.7 TIM Channel 2 Interrupt (CH2)704.6.2.8 TIM Channel 3 Interrupt (CH3)704.6.2.9 TIM Timer Overflow Interrupt (TOV)704.6.2.10 SCI Error Interrupt (ERR)704.6.2.11 SCI Transmit Interrupt (TX)704.6.2.12 SCI Receive Interrupt (RX)704.6.2.13 LIN Driver Over-temperature Interrupt (LINOT)704.6.2.14 High Side Over-temperature Interrupt (HSOT)704.6.2.15 Low Side Over-temperature Interrupt (LSOT)704.6.2.16 HSUP Over-temperature Interrupt (HOT)704.6.2.17 High Voltage Interrupt (HVI)704.6.2.18 Voltage Regulator Over-voltage Interrupt (VROVI)714.7 Resets714.7.1 Reset Sources714.7.1.1 POR - Analog Die Power On Reset714.7.1.2 LVR - Low Voltage Reset - VDD714.7.1.3 LVRX - Low Voltage Reset - VDDX714.7.1.4 WUR - Wake-up Reset714.7.1.5 EXR - External Reset714.7.1.6 WDR - Watchdog Reset714.7.2 Register Definition724.7.2.1 Reset Status Register (RSR)724.8 Wake-up / Cyclic Sense734.8.1 Wake-up Sources734.8.1.1 Lx - Wake-up (Cyclic Sense Disabled)734.8.1.2 Lx - Cyclic Sense Wake-up744.8.1.3 Forced Wake-up744.8.1.4 LIN - Wake-up744.8.1.5 D2D - Wake-up (Stop Mode only)744.8.1.6 Wake-up Due to Internal / External Reset (STOP Mode Only)744.8.1.7 Wake-up Due to Loss of Supply Voltage (SLEEP Mode Only)744.8.2 Register Definition754.8.2.1 Wake-up Control Register (WCR)754.8.2.2 Timing Control Register (TCR)764.8.2.3 Wake-up Source Register (WSR)774.9 Window Watchdog784.9.1 Register Definition794.9.1.1 Watchdog Register (WDR)794.9.1.2 Watchdog Service Register (WDSR)794.10 Hall Sensor Supply Output - HSUP804.10.1 Register Definition804.10.1.1 Hall Supply Register (HSR)804.11 High Side Drivers - HS814.11.1 Open Load Detection814.11.2 Current Limitation814.11.3 Over-temperature Protection (HS Interrupt)814.11.4 High Voltage Shutdown814.11.5 Sleep And Stop Mode814.11.6 PWM Capability814.11.7 Register Definition824.11.7.1 High Side Control Register (HSCR)824.11.7.2 High Side Status Register (HSSR)834.12 Low Side Drivers - LSx844.12.1 Introduction / Features844.12.1.1 Block Diagram844.12.1.2 Modes of Operation844.12.2 External Signal Description854.12.3 Memory Map and Registers854.12.3.1 Module Memory Map854.12.3.2 Register Descriptions854.12.3.2.1 Low Side Control Register (LSCR)854.12.3.2.2 Low Side Status Register (LSSR)864.12.3.2.3 Low Side Control Enable Register (LSCEN)864.12.4 Functional Description884.12.4.1 Voltage Regulator Over-voltage Protection884.12.4.2 Open Load Detection884.12.4.3 Current Limitation884.12.4.4 Over-temperature Protection (LS Interrupt)884.12.5 PWM Capability894.13 PWM Control Module (PWM8B2C)904.13.1 Introduction904.13.1.1 Features904.13.1.2 Modes of Operation904.13.1.3 Block Diagram914.13.2 Signal Description914.13.2.1 D2DCLK914.13.2.2 PWM1 — Pulse Width Modulator Channel 1914.13.2.3 PWM0 — Pulse Width Modulator Channel 0914.13.3 Register Descriptions924.13.3.1 PWM Control Register (PWMCTL)924.13.3.1.1 PWM Enable (PWMEx)934.13.3.1.2 PWM Polarity (PPOLx)934.13.3.1.3 PWM Clock Select (PCLKx)934.13.3.1.4 PWM Center Align Enable (CAEx)944.13.3.2 PWM Prescale Clock Select Register (PWMPRCLK)944.13.3.3 PWM Scale A Register (PWMSCLA)954.13.3.4 PWM Scale B Register (PWMSCLB)954.13.3.5 PWM Channel Counter Registers (PWMCNTx)964.13.3.6 PWM Channel Period Registers (PWMPERx)974.13.3.7 PWM Channel Duty Registers (PWMDTYx)984.13.4 Functional Description994.13.4.1 PWM Clock Select994.13.4.1.1 Prescale994.13.4.1.2 Clock Scale994.13.4.1.3 Clock Select1014.13.4.2 PWM Channel Timers1014.13.4.2.1 PWM Enable1024.13.4.2.2 PWM Polarity1024.13.4.2.3 PWM Period and Duty1034.13.4.2.4 PWM Timer Counters1034.13.4.2.5 Left Aligned Outputs1044.13.4.2.6 Center Aligned Outputs1054.13.4.2.7 PWM Boundary Cases1064.13.5 Resets1064.13.6 Interrupts1064.14 LIN Physical Layer Interface - LIN1074.14.1 LIN Pin1074.14.2 Slew Rate Selection1074.14.3 Over-temperature Shutdown (LIN Interrupt)1074.14.4 Low Power Mode and Wake-up Feature1074.14.5 J2602 Compliance1074.14.6 Register Definition1084.14.6.1 LIN Register (LINR)1084.15 Serial Communication Interface (S08SCIV4)1094.15.1 Introduction1094.15.1.1 Features1094.15.1.2 Modes of Operation1094.15.1.3 Block Diagram1104.15.2 Register Definition1124.15.2.1 SCI Baud Rate Registers (SCIBD (hi), SCIBD (lo))1124.15.2.2 SCI Control Register 1 (SCIC1)1134.15.2.3 SCI Control Register 2 (SCIC2)1144.15.2.4 SCI Status Register 1 (SCIS1)1154.15.2.5 SCI Status Register 2 (SCIS2)1164.15.2.6 SCI Control Register 3 (SCIC3)1174.15.2.7 SCI Data Register (SCID)1184.15.3 Functional Description1184.15.3.1 Baud Rate Generation1184.15.3.2 Transmitter Functional Description1194.15.3.2.1 Send Break and Queued Idle1194.15.3.3 Receiver Functional Description1204.15.3.3.1 Data Sampling Technique1204.15.3.3.2 Receiver Wake-up Operation1204.15.3.3.2.1 Idle-line Wake-up1214.15.3.3.2.2 Address-Mark Wake-up1214.15.3.4 Interrupts and Status Flags1214.15.3.5 Additional SCI Functions1224.15.3.5.1 8- and 9-Bit Data Modes1224.15.3.5.2 Stop Mode Operation1224.15.3.5.3 Loop Mode1224.15.3.5.4 Single-wire Operation1224.16 High Voltage Inputs - Lx1234.16.1 Register Definition1234.16.1.1 Lx Status Register (LXR)1234.16.1.2 Lx Control Register (LXCR)1234.17 General Purpose I/O - PTB[0…2]1244.17.1 Digital I/O Functionality1244.17.2 Alternative SCI / LIN Functionality1244.17.3 Alternative PWM Functionality1244.17.4 Register definition1254.17.4.1 Port B Configuration Register 1 (PTBC1)1254.17.4.2 Port B Configuration Register 2 (PTBC2)1254.17.4.3 Port B Data Register (PTB)1264.18 Basic Timer Module - TIM (TIM16B4C)1274.18.1 Introduction1274.18.1.1 Overview1274.18.1.2 Features1274.18.1.3 Modes of Operation1274.18.1.4 Block Diagram1274.18.2 Signal Description1284.18.2.1 Overview1284.18.2.2 Detailed Signal Descriptions1284.18.2.2.1 IOC3 – Input Capture and Output Compare Channel 31284.18.2.2.2 IOC2 – Input Capture and Output Compare Channel 21284.18.2.2.3 IOC1 – Input Capture and Output Compare Channel 11284.18.2.2.4 IOC0 – Input Capture and Output Compare Channel 01284.18.3 Memory Map and Registers1284.18.3.1 Overview1284.18.3.2 Module Memory Map1284.18.3.3 Register Descriptions1304.18.3.3.1 Timer Input Capture/Output Compare Select (TIOS)1304.18.3.3.2 Timer Compare Force Register (CFORC)1304.18.3.3.3 Output Compare 3 Mask Register (OC3M)1314.18.3.3.4 Output Compare 3 Data Register (OC3D)1314.18.3.3.5 Timer Count Register (TCNT)1324.18.3.3.6 Timer System Control Register 1 (TSCR1)1324.18.3.3.7 Timer Toggle On Overflow Register 1 (TTOV)1334.18.3.3.8 Timer Control Register 1 (TCTL1)1344.18.3.3.9 Timer Control Register 2 (TCTL2)1344.18.3.3.10 Timer Interrupt Enable Register (TIE)1354.18.3.3.11 Timer System Control Register 2 (TSCR2)1354.18.3.3.12 Main Timer Interrupt Flag 1 (TFLG1)1364.18.3.3.13 Main Timer Interrupt Flag 2 (TFLG2)1374.18.3.3.14 Timer Input Capture/Output Compare Registers (TC3 - TC0)1374.18.4 Functional Description1394.18.4.1 General1394.18.4.2 Prescaler1394.18.4.3 Input Capture1404.18.4.4 Output Compare1404.18.5 Resets1404.18.5.1 General1404.18.6 Interrupts1404.18.6.1 General1404.18.6.2 Description of Interrupt Operation1414.18.6.2.1 Channel [3:0] Interrupt1414.18.6.2.2 Timer Overflow Interrupt (TOF)1414.19 Analog Digital Converter - ADC1424.19.1 Introduction1424.19.1.1 Overview1424.19.1.2 Features1424.19.2 Modes of Operation1424.19.3 External Signal Description1434.19.4 Memory Map and Register Definition1434.19.4.1 Module Memory Map1434.19.4.2 Register Definition1454.19.4.2.1 ADC Config Register (ACR)1454.19.4.2.2 ADC Status Register (ASR)1464.19.4.2.3 ADC Conversion Control Register (ACCR)1464.19.4.2.4 ADC Conversion Complete Status Register (ACCSR)1474.19.4.2.5 ADC Data Result Register x (ADRx)1474.19.5 Functional Description1484.19.5.1 Analog Channel Definitions1484.19.5.2 Automatic Offset Compensation1484.19.5.3 Conversion Timing1494.20 Current Sense Module - ISENSE1504.20.1 Register Definition1504.20.1.1 Current Sense Register (CSR)1504.21 Temperature Sensor - TSENSE1524.22 Supply Voltage Sense - VSENSE1534.23 Internal Supply Voltage Sense - VS1SENSE1534.24 Internal Bandgap Reference Voltage Sense - BANDGAP1534.25 MM912F634 - Analog Die Trimming1544.25.1 Memory Map and Register Definition1544.25.1.1 Module Memory Map1544.25.1.2 Register Descriptions1554.25.1.2.1 Trimming Register 0 (CTR0)1554.25.1.2.2 Trimming Register 1 (CTR1)1554.25.1.2.3 Trimming Register 2 (CTR2)1564.25.1.2.4 Trimming Register 3 (CTR3)1574.26 MM912F634 - MCU Die Overview1584.26.1 Introduction1584.26.1.1 Features1584.26.1.2 Modes of Operation1594.26.2 Block Diagrams1594.26.3 Device Memory Map1594.26.3.1 Address Mapping1594.26.4 Part ID Assignments1624.26.5 System Clock Description1624.26.6 Modes of Operation1634.26.6.1 Chip Configuration Summary1634.26.6.1.1 Normal Single-chip Mode1634.26.6.1.2 Special Single-chip Mode1634.26.6.2 Power Modes1634.26.6.2.1 System Stop Mode1644.26.6.2.2 Wait Mode1644.26.6.2.3 Run Mode1644.26.6.2.4 Freeze Mode1644.26.7 Security1644.26.7.1 MC9S12I321644.26.8 Resets and Interrupts1644.26.8.1 Resets1644.26.8.2 Vectors1644.26.8.3 Effects of Reset1654.26.8.3.1 I/O Pins1654.26.8.3.2 Memory1654.27 Port Integration Module (9S12I32PIMV1)1664.27.1 Introduction1664.27.2 Features1664.27.3 Memory Map1664.27.3.1 Port A Data Register (PTA)1684.27.3.2 PIM Reserved Register1694.27.3.3 Port A Data Direction Register (DDRA)1694.27.3.4 PIM Reserved Register1694.27.3.5 Port C Data Register (PTC)1704.27.3.6 Port D Data Register (PTD)1704.27.3.7 Port C Data Direction Register (DDRC)1714.27.3.8 Port D Data Direction Register (DDRD)1714.27.3.9 PIM Reserved Registers1724.27.3.10 Port A Input Register (PTIA)1724.27.3.11 PIM Reserved Register1724.27.3.12 Port A Reduced Drive Register (RDRA)1734.27.3.13 PIM Reserved Registers1734.27.4 Functional Description1744.27.4.1 General1744.27.4.2 Registers1744.27.4.2.1 Data register (PTx)1744.27.4.2.2 Data direction register (DDRx)1744.27.4.2.3 Input register (PTIx)1744.27.4.2.4 Reduced drive register (RDRx)1744.27.4.3 Ports1754.27.4.3.1 Port A1754.27.4.3.2 Port C1754.27.4.3.3 Port D1754.27.5 Initialization Information1754.27.5.1 Port Data and Data Direction Register writes1754.28 Memory Mapping Control (S12SMMCV1)1764.28.1 Introduction1764.28.1.1 Terminology1764.28.1.2 Features1764.28.1.3 S12S Memory Mapping1774.28.1.4 Modes of Operation1774.28.1.4.1 Power Saving Modes1774.28.1.4.2 Functional Modes1774.28.1.5 Block Diagram1774.28.2 Memory Map and Registers1784.28.2.1 Module Memory Map1784.28.2.2 Register Descriptions1784.28.2.2.1 Program Page Index Register (PPAGE)1784.28.2.2.2 Direct Page Register (DIRECT)1794.28.2.2.3 Mode Register (MODE)1814.28.2.2.4 MMC Control Register (MMCCTL1)1824.28.3 Functional Description1824.28.3.1 MCU Operating Mode1824.28.3.2 Memory Map Scheme1824.28.3.2.1 CPU and BDM Memory Map Scheme1824.28.3.2.2 Expansion of the Local Address Map1834.28.3.2.2.1 Expansion of the CPU Local Address Map1834.28.3.2.2.2 Expansion of the BDM Local Address Map1834.28.3.2.3 Implemented Memory Map1844.28.3.3 Chip Bus Control1884.28.3.3.1 Master Bus Prioritization Regarding Access Conflicts on Target Buses1884.28.3.4 Interrupts1884.28.4 Initialization/Application Information1894.28.4.1 CALL and RTC Instructions1894.29 Interrupt Module (S12SINTV1)1904.29.1 Introduction1904.29.1.1 Glossary1904.29.1.2 Features1904.29.1.3 Modes of Operation1904.29.1.4 Block Diagram1914.29.2 External Signal Description1914.29.3 Memory Map and Register Definition1914.29.3.1 Register Descriptions1914.29.3.1.1 Interrupt Vector Base Register (IVBR)1914.29.4 Functional Description1924.29.4.1 S12S Exception Requests1924.29.4.2 Interrupt Prioritization1924.29.4.3 Reset Exception Requests1924.29.4.4 Exception Priority1934.29.5 Initialization/Application Information1934.29.5.1 Initialization1934.29.5.2 Interrupt Nesting1934.29.5.3 Wake-up from Stop or Wait Mode1944.29.5.3.1 CPU Wake-up from Stop or Wait Mode1944.30 Background Debug Module (S12SBDMV1)1954.30.1 Introduction1954.30.1.1 Features1954.30.1.2 Modes of Operation1954.30.1.2.1 Regular Run Modes1954.30.1.2.2 Secure Mode Operation1964.30.1.2.3 Low Power Modes1964.30.1.3 Block Diagram1964.30.2 External Signal Description1974.30.3 Memory Map and Register Definition1974.30.3.1 Module Memory Map1974.30.3.2 Register Descriptions1974.30.3.2.1 BDM Status Register (BDMSTS)1984.30.3.2.2 BDM Status Register (BDMSTS)1984.30.3.2.3 BDM Program Page Index Register (BDMPPR)2004.30.3.3 Family ID Assignment2004.30.4 Functional Description2004.30.4.1 Security2014.30.4.2 Enabling and Activating BDM2014.30.4.3 BDM Hardware Commands2024.30.4.4 Standard BDM Firmware Commands2034.30.4.5 BDM Command Structure2044.30.4.6 BDM Serial Interface2054.30.4.7 Serial Interface Hardware Handshake Protocol2074.30.4.8 Hardware Handshake Abort Procedure2094.30.4.9 SYNC — Request Timed Reference Pulse2114.30.4.10 Instruction Tracing2124.30.4.11 Serial Communication Timeout2134.31 S12S Debug (S12SDBGV1) Module2144.31.1 Introduction2144.31.1.1 Glossary Of Terms2144.31.1.2 Overview2144.31.1.3 Features2144.31.1.4 Modes of Operation2154.31.1.5 Block Diagram2154.31.2 External Signal Description2164.31.3 Memory Map and Registers2164.31.3.1 Module Memory Map2164.31.3.2 Register Descriptions2174.31.3.2.1 Debug Control Register 1 (DBGC1)2174.31.3.2.2 Debug Status Register (DBGSR)2184.31.3.2.3 Debug Trace Control Register (DBGTCR)2194.31.3.2.4 Debug Control Register2 (DBGC2)2204.31.3.2.5 Debug Trace Buffer Register (DBGTBH:DBGTBL)2204.31.3.2.6 Debug Count Register (DBGCNT)2214.31.3.2.7 Debug State Control Registers2224.31.3.2.7.1 Debug State Control Register 1 (DBGSCR1)2224.31.3.2.7.2 Debug State Control Register 2 (DBGSCR2)2234.31.3.2.7.3 Debug State Control Register 3 (DBGSCR3)2244.31.3.2.7.4 Debug Match Flag Register (DBGMFR)2254.31.3.2.8 Comparator Register Descriptions2254.31.3.2.8.1 Debug Comparator Control Register (DBGXCTL)2264.31.3.2.8.2 Debug Comparator Address High Register (DBGXAH)2274.31.3.2.8.3 Debug Comparator Address Mid Register (DBGXAM)2284.31.3.2.8.4 Debug Comparator Address Low Register (DBGXAL)2294.31.3.2.8.5 Debug Comparator Data High Register (DBGADH)2294.31.3.2.8.6 Debug Comparator Data Low Register (DBGADL)2304.31.3.2.8.7 Debug Comparator Data High Mask Register (DBGADHM)2304.31.3.2.8.8 Debug Comparator Data Low Mask Register (DBGADLM)2314.31.4 Functional Description2314.31.4.1 S12SDBGV1 Operation2314.31.4.2 Comparator Modes2324.31.4.2.1 Exact Address Comparator Match (Comparators A and C)2334.31.4.2.2 Exact Address Comparator Match (Comparator B)2334.31.4.2.3 Range Comparisons2344.31.4.2.3.1 Inside Range (CompA_Addr £ address £ CompB_Addr)2344.31.4.2.3.2 Outside Range (address < CompA_Addr or address > CompB_Addr)2344.31.4.3 Match Modes (Forced or Tagged)2344.31.4.3.1 Forced Match2344.31.4.3.2 Tagged Match2344.31.4.3.3 Immediate Trigger2344.31.4.3.4 Channel Priorities2354.31.4.4 State Sequence Control2354.31.4.4.1 Final State2364.31.4.5 Trace Buffer Operation2364.31.4.5.1 Trace Trigger Alignment2364.31.4.5.1.1 Storing with Begin Trigger2364.31.4.5.1.2 Storing with End Trigger2364.31.4.5.2 Trace Modes2364.31.4.5.3 Normal Mode2374.31.4.5.3.1 Loop1 Mode2384.31.4.5.3.2 Detail Mode2384.31.4.5.3.3 Pure PC Mode2384.31.4.5.4 Trace Buffer Organization2394.31.4.5.4.1 Information Bit Organization2394.31.4.5.4.2 Field2 Bits in Detail Mode2394.31.4.5.4.3 Field2 Bits in Normal, Pure PC and Loop1 Modes2404.31.4.5.5 Reading Data from Trace Buffer2404.31.4.5.6 Trace Buffer Reset State2404.31.4.6 Tagging2414.31.4.7 Breakpoints2414.31.4.7.1 Breakpoints From Comparator Channels2414.31.4.7.2 Breakpoints Generated Via the TRIG Bit2424.31.4.7.3 Breakpoint Priorities2424.31.4.7.3.1 DBG Breakpoint Priorities and BDM Interfacing2424.32 S12S Clocks and Reset Generator (S12SCRGV1)2434.32.1 Introduction2434.32.1.1 Features2434.32.1.2 Modes of Operation2434.32.1.2.1 Run Mode2434.32.1.2.2 Wait Mode2444.32.1.2.3 Stop Mode2444.32.1.3 Block Diagram2444.32.2 Signal Description2454.32.2.1 RESET2454.32.3 Memory Map and Registers2464.32.3.1 Module Memory Map2464.32.3.2 Register Descriptions2464.32.3.2.1 9S12I32PIMV1 Control Register 0 (CRGCTL0)2474.32.3.2.2 9S12I32PIMV1 Control Register 1 (CRGCTL1)2484.32.3.2.3 9S12I32PIMV1 FLL Multiply Register (CRGMULT)2484.32.3.2.4 9S12I32PIMV1 Flags Register (CRGFLG)2494.32.3.2.5 9S12I32PIMV1TRIM register (CRGTRIMH, CRGTRIML)2504.32.3.2.6 9S12I32PIMV1 Test Register 0 (CRGTEST0)2504.32.3.2.7 9S12I32PIMV1 Test Register 1 (CRGTEST1)2514.32.4 Write: Not Possible Functional Description2514.32.4.1 Startup from Reset2514.32.4.2 Stop Mode Using DCO Clock as a Bus Clock2524.32.4.3 Stop Mode Using Oscillator Clock as Bus Clock2524.32.4.4 Enabling the External Oscillator2534.32.5 Resets2534.32.5.1 General2534.32.5.2 Description of Reset Operation2544.32.5.2.1 Oscillator Monitor Reset2544.32.5.2.2 Computer Operating Properly Watchdog (COP) Reset2554.32.5.2.3 Power-On Reset2554.32.6 Interrupts2554.32.6.1 Description of Interrupt Operation2554.32.6.1.1 FLL Lock Interrupt2554.33 External Oscillator (S12SS12SCRGV1)2564.33.1 Introduction2564.33.2 Features2564.33.3 Modes of Operation2564.33.4 Block Diagram2564.33.5 External Signals EXTAL and XTAL — Input and Output Pins2574.34 Real Time Interrupt (S12SRTIV1)2584.34.1 Introduction2584.34.2 Overview2584.34.3 Features2584.34.4 Modes of Operation2584.34.5 External Signal Description2584.34.6 Memory Map and Register2594.34.6.1 Module Memory Map2594.34.6.2 Register Descriptions2594.34.6.2.1 RTI Control Register (RTICTL)2594.34.6.2.2 RTI Counter select bits (RTICNT)2604.34.7 Functional Description2614.34.7.1 RTI register write protection rules2614.34.7.2 Modification of Prescaler rate (RTIRT bits)2614.34.7.3 Modification of Modulus Down Counter rate (RTICNT register)2624.35 Computer Operating Properly (S12SCOPV1)2634.35.1 Introduction2634.35.1.1 Overview2634.35.1.2 Features2634.35.1.3 Modes of Operation2644.35.2 External Signal Description2644.35.3 Memory Map and Register2644.35.3.1 Module Memory Map2644.35.3.2 Register Descriptions2644.35.3.2.1 COP Control Register (COPCTL)2654.35.3.2.2 COP Timer Arm/Reset Register (ARMCOP)2674.35.4 Functional Description2674.35.4.1 COP Configuration2684.36 32 kbyte Flash Module (S12SFTSR32KV1)2694.36.1 Introduction2694.36.1.1 Glossary2694.36.1.2 Features2694.36.1.3 Block Diagram2704.36.2 External Signal Description2704.36.3 Memory Map and Register Definition2714.36.3.1 Flash Array Map2714.36.3.1.1 Flash Configuration Field Description2714.36.3.2 Flash IFR Map2724.36.3.3 Register Descriptions2724.36.3.3.1 Flash Clock Divider Register (FCLKDIV)2734.36.3.3.2 Flash Security Register (FSEC)2744.36.3.3.3 Flash Reserved0 Register (FRSV0)2754.36.3.3.4 Flash Configuration Register (FCNFG)2754.36.3.3.5 Flash Protection Register (FPROT)2764.36.3.4 Flash Status Register (FSTAT)2784.36.3.4.1 Flash Command Register (FCMD)2794.36.3.4.2 Flash Reserved1 Register (FRSV1)2804.36.3.4.3 Flash Address Registers (FADDR)2804.36.3.4.4 Flash Data Registers (FDATA)2814.36.3.4.5 Flash Reserved2 Register (FRSV2)2824.36.3.4.6 Flash Reserved3 Register (FRSV3)2824.36.3.4.7 Flash Reserved4 Register (FRSV4)2824.36.3.4.8 Flash Reserved5 Register (FRSV5)2834.36.3.4.9 Flash Option Register (FOPT)2834.36.4 Functional Description2834.36.4.1 Flash Command Operations2834.36.4.1.1 Writing the FCLKDIV Register2844.36.4.1.2 Command Write Sequence2854.36.4.2 Flash Commands2864.36.4.2.1 Erase Verify Command2874.36.4.2.2 Program Command2884.36.4.2.3 Burst Program Command2894.36.4.2.4 Sector Erase Command2924.36.4.2.5 Mass Erase Command2944.36.4.2.6 Set Verify Margin Level Command2954.36.4.3 Illegal Flash Operations2964.36.4.3.1 Flash Access Violations2964.36.4.3.2 Flash Protection Violations2974.36.5 Operating Modes2974.36.5.1 Wait Mode2974.36.5.2 Stop Mode2974.36.5.3 Background Debug Mode2984.36.6 Flash Module Security2984.36.6.1 Unsecuring the MCU Using Backdoor Key Access2984.36.6.2 Unsecuring the MCU in Special Mode Using BDM2994.36.7 Resets2994.36.7.1 Flash Reset Sequence2994.36.7.2 Reset While Flash Command Active2994.36.8 Interrupts2994.36.8.1 Description of Flash Interrupt Operation3004.37 Die-to-Die Initiator (D2DIV1)3014.37.1 Introduction3014.37.1.1 Overview3014.37.1.2 Features3014.37.1.3 Modes of Operation3024.37.1.3.1 D2DI in STOP/WAIT Mode3024.37.1.3.2 D2DI in special modes3024.37.2 External Signal Description3024.37.2.1 D2DCLK3024.37.2.2 D2DDAT[7:4]3024.37.2.3 D2DDAT[3:0]3024.37.2.4 D2DINT3024.37.3 Memory Map and Register Definition3034.37.3.1 Memory Map3034.37.3.2 Register Definition3044.37.3.2.1 D2DI Control Register 0 (D2DCTL0)3044.37.3.2.2 D2DI Control Register 1 (D2DCTL1)3054.37.3.2.3 D2DI Status Register 0 (D2DSTAT0)3064.37.3.2.4 D2DI Status Register 1 (D2DSTAT1)3064.37.3.2.5 D2DI Address Buffer Register (D2DADR)3074.37.3.2.6 D2DI Data Buffer Register (D2DDATA)3084.37.4 Functional Description3084.37.4.1 Initialization3084.37.4.2 Transactions3084.37.4.2.1 Blocking Writes3094.37.4.2.2 Non-blocking Writes3094.37.4.2.3 Blocking Read3104.37.4.2.4 Non-blocking Read3104.37.4.3 Transfer Width3104.37.4.4 Error Conditions and Handling faults3104.37.4.4.1 Missing Acknowledge3104.37.4.4.2 Parity error3104.37.4.4.3 Error Signal3104.37.4.5 Low Power Mode Options3114.37.4.5.1 D2DI in Run Mode3114.37.4.5.2 D2DI in Wait Mode3114.37.4.5.3 D2DI in Stop Mode3114.37.4.6 Reset3114.37.4.7 Interrupts3114.37.4.7.1 D2D External Interrupt3114.37.4.7.2 D2D Error Interrupt3114.37.5 Initialization Information3124.37.6 Application Information3124.37.6.1 Entering low power mode3124.38 Serial Peripheral Interface (S12SPIV4)3134.38.1 Introduction3134.38.1.1 Glossary of Terms3134.38.1.2 Features3134.38.1.3 Modes of Operation3134.38.1.4 Block Diagram3144.38.2 External Signal Description3144.38.2.1 MOSI — Master Out/Slave In Pin3144.38.2.2 MISO — Master In/Slave Out Pin3144.38.2.3 SS — Slave Select Pin3154.38.2.4 SCK — Serial Clock Pin3154.38.3 Memory Map and Register Definition3154.38.3.1 Module Memory Map3154.38.3.2 Register Descriptions3154.38.3.2.1 SPI Control Register 1 (SPICR1)3164.38.3.2.2 SPI Control Register 2 (SPICR2)3174.38.3.2.3 SPI Baud Rate Register (SPIBR)3184.38.3.2.4 SPI Status Register (SPISR)3204.38.3.2.5 SPI Data Register (SPIDR)3214.38.4 Functional Description3224.38.4.1 Master Mode3234.38.4.2 Slave Mode3244.38.4.3 Transmission Formats3254.38.4.3.1 Clock Phase and Polarity Controls3254.38.4.3.2 CPHA = 0 Transfer Format3254.38.4.3.3 CPHA = 1 Transfer Format3274.38.4.4 SPI Baud Rate Generation3284.38.4.5 Special Features3294.38.4.5.1 SS Output3294.38.4.5.2 Bidirectional Mode (MOMI or SISO)3294.38.4.6 Error Conditions3304.38.4.6.1 Mode Fault Error3304.38.4.7 Low Power Mode Options3314.38.4.7.1 SPI in Run Mode3314.38.4.7.2 SPI in Wait Mode3314.38.4.7.3 SPI in Stop Mode3314.38.4.7.4 Reset3324.38.4.7.5 Interrupts3324.38.4.7.5.1 MODF3324.38.4.7.5.2 SPIF3324.38.4.7.5.3 SPTEF3325 Packaging3335.1 Package Dimensions3336 Revision History338Größe: 4,51 MBSeiten: 339Language: EnglishHandbuch öffnen
Benutzerhandbuch (KIT912F634EVME)InhaltsverzeichnisKIT912F634EVME Evaluation Board1Featuring the MM912F634 Integrated S12-Based Relay Driver with LIN Device11 Kit Contents/Packing List22 Jump Start33 Important Notice44 KIT912F634EVME Introduction54.1 MM912F634 Features54.2 Caution54.3 Acronyms65 Required Equipment66 Setup Guide66.1 Hardware Setup67 Hardware Description87.1 Board Description87.1.1 MCU97.1.2 TBDML97.2 Jumper Settings97.3 Connector Description117.3.1 Connectors117.3.2 LIN Connector J1127.3.3 Power Connectors J2, J3127.3.4 BDM Connector J4127.3.5 Signal Connector J5137.3.6 Signal Connector J6137.3.7 Signal Connector J7147.3.8 Signal Connector J8147.3.9 USB Connector J101157.3.10 TBDML Programming Connector J102157.4 Test Points158 Software Description168.1 Software Setup168.1.1 FreeMASTER Software Installation168.1.2 FreeMASTER Software Setup178.2 Important Notes on Programming and Debugging of the Board178.2.1 Hardware Considerations178.2.2 Programming and Debugging via the TBDML Interface178.2.3 Programming and Debugging via BDM Interface178.3 FreeMASTER Graphical User Interface188.3.1 About the FreeMASTER Software188.3.2 FreeMASTER Software on the Embedded Side188.3.2.1 General Outline188.3.2.2 FreeMASTER with the KIT912F634EVME198.3.3 FreeMASTER Software on the PC198.3.4 Graphical User Interface198.3.4.1 Start of the GUI and Troubleshooting (via TBDML)208.3.4.2 Start of the GUI and Troubleshooting (via BDM)248.3.4.3 FreeMASTER Direct Register Access Page268.3.4.4 FreeMASTER Analog Die Module Access Page278.3.4.5 Status Block288.3.4.6 LIN Module298.3.4.7 High Side and Low Side Switch Control, and PWM Module298.3.4.8 ADC Module Control Frame308.3.4.9 Low Power Modes - STOP Mode and SLEEP Mode308.4 Embedded Software318.4.1 Main Software Flow Chart318.4.2 FreeMASTER Variables328.4.2.1 Performing the FreeMASTER Variables Update328.4.3 LIN Communication338.4.3.1 Change of the LIN Communication Parameters339 Schematics3410 Board Layout3610.1 Assembly Layer Top3610.2 Assembly Layer Bottom3710.3 Top Layer Routing3810.4 Bottom Layer Routing3911 Bill of Materials4012 References4312.1 Support4312.2 Warranty4313 Revision History44Größe: 4,49 MBSeiten: 46Language: EnglishHandbuch öffnen
