Freescale Semiconductor KIT912F634EVME Evaluation Kit KIT912F634EVME KIT912F634EVME Datenbogen

Freescale Semiconductor

30

 summarizes several startup characteristics explained in this section. Detailed description of the startup behavior can be 

found in the Clock and Reset Generator (CRG) block description.

Internal Reference Frequency

 (-40

C  T

J

 

 105 C)

f

IREF_TRIM

31.36

32

32.64

kHz

Internal Reference Frequency

 (-40

C  T

J

 

 140 C)

f

IREF_TRIM

30.40

32

33.60

kHz

Allowed frequency range for FLL Reference Clock

f

FLLREF

25.52

-

40

kHz

DCO Frequency locking range

f

DCO

32

-

40

MHz

DCO minimum frequency

f

DCO_MIN

18

-

29

MHz

DCO stabilization delay in frequency locked loop

t

STAB

-

0.3

-

ms

Lock Detection

| 



LOCK

 |

0

-

1.5

%

Un-lock Detection

| 



UNLOCCK

 |

0.5

-

2.5

%

DCO quantization error

t

DCO

-

-

0.2

%t

DCO

STOP recovery time
(Internal Reference Clock trimmed to 32 kHz)

t

STP_REC

-

20

-

s

Oscillator Monitor Failure Assert Frequency

f

OMFA

50

-

200

kHz

Reset input pulse width, minimum input time

PW

RSTL

2.0

-

-

t

DCO_MIN

Startup from Reset

n

RST

772

-

773

t

DCO_MIN

Note:

48. Reference Frequency is factory trimmed
49. % deviation from target frequency, target frequency is f

IREF_TRIM

 * (1000 + 2*MULT[6:0])

50. f

DCO =

40 MHz, f

IREF_TRIM =

32 kHz, MULT = $7D