Freescale Semiconductor KIT912F634EVME Evaluation Kit KIT912F634EVME KIT912F634EVME Datenbogen

Freescale Semiconductor

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When reading from the address window associated with blocking transactions, the CPU is held until the data is returned from the 
target, before completing the instruction.

 shows the behavior of the CPU for a blocking read transaction shown in the 

following example.

LDAA

BLK_WINDOW+OFFS0 ; Read 8-bit as a blocking transaction

STAA

MEM

; Store result to local Memory

LDAA

BLK_WINDOW+OFFS1 ; Read 8-bit as a blocking transaction

Read access to the non-blocking window is reserved for future use. When reading from the address window associated with 
non-blocking writes, the read returns an all 0s data byte or word. This behavior can change in future revisions.

8-bit wide writes or reads are translated into 8-bit wide interface transactions. 16-bit wide, aligned writes or reads are translated 
into 16-bit wide interface transactions. 16-bit wide, misaligned writes or reads are split up into two consecutive 8-bit transactions, 
with the transaction on the odd address first followed by the transaction on the next higher even address. Due to the much more 
complex error handling (by the MCU), misaligned 16-bit transfers should be avoided.

Since the S12 CPU (as well as the S08) do not provide a method to abort a transfer once started, the D2DI asserts an 
D2DERRINT. The ERRIF Flag is set in the D2DSTAT0 register. Depending on the error condition, further error flags will be set 
as described below. The content of the address and data buffers are frozen, and all transactions will be replaced by an IDLE 
command, until the error flag is cleared. If an error is detected during the read transaction of a read-modify-write instruction, or 
a non-blocking write transaction was followed by another write or read transaction, the second transaction is cancelled. The 
CNCLF is set in the D2DSTAT0 register to indicate that a transaction has been cancelled. The D2DERRINT handler can read 
the address and data buffer register to assess the error situation. Any further transaction will be replaced by IDLE until the ERRIF 
is cleared.

If the target detects a wrong command, it will not send back an acknowledge. The same situation occurs if the acknowledge is 
corrupted. The D2DI detects this missing acknowledge after the timeout period configured in the TIMOUT parameter of the 
D2DCTL1 register. In case of a timeout, the ERRIF and the TIMEF flags in the D2DSTAT0 register will be set.

In the final acknowledge cycle of a transaction, the target sends two parity bits. If this parity does not match the parity calculated 
by the initiator, the ERRIF and the PARF flags in the D2DSTAT0 register will be set. The PAR[1:0] bits contain the parity value 
received by the D2DI.

During the acknowledge cycle the target can signal a target specific error condition. If the D2DI finds the error signal asserted 
during a transaction, the ERRIF and the TERRF flags in the D2DSTAT0 register will be set.