Freescale Semiconductor MC56F8006 Demo board MC56F8006DEMO MC56F8006DEMO Datenbogen
Produktcode
MC56F8006DEMO
Signal/Connection Descriptions
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
17
Figure 7. Top View, MC56F8006 48-Pin LQFP Package
4.3
56F8006/56F8002 Signal Pins
After reset, each pin is configured for its primary function (listed first). Any alternate functionality must be programmed via the
GPIO module’s peripheral enable registers (GPIO_x_PER) and SIM module’s (GPS_xn) GPIO peripheral select registers. If
CLKIN or XTAL is selected as device external clock input, the CLK_MOD bit in the OCCS oscillator control register (OSCTL)
needs to be set too. EXT_SEL bit in OSCTL selects CLKIN or XTAL.
GPIO module’s peripheral enable registers (GPIO_x_PER) and SIM module’s (GPS_xn) GPIO peripheral select registers. If
CLKIN or XTAL is selected as device external clock input, the CLK_MOD bit in the OCCS oscillator control register (OSCTL)
needs to be set too. EXT_SEL bit in OSCTL selects CLKIN or XTAL.
Orientation Mark
GPIOB6/RXD/SDA/ANA13 & CMP0_P2/CLKIN
GPIOB1/SS/SDA/ANA12 & CMP2_P3
GPIOB7/TXD/SCL/ANA11 & CMP2_M3
GPIOB5/T1/FAULT3/SCLK
ANB8 and PGA1+ & CMP0_M2/GPIOC4
ANB6 and PGA1– & CMP0_P4/GPIOC5
ANB4 & CMP1_P1/GPIOC6/PWM2
V
DDA
V
SSA
A
N
A9
and
PG
A0–
&
CMP2
_P4/
GP
IO
C2
AN
A
7
&
P
G
A0
+
&
C
M
P2
_
M
2
/G
P
IO
C
1
ANA5 & CMP1_
M
1
/G
P
IO
C0/
F
A
U
LT
0
V
SS
TCK/
GP
IO
D
2
/A
NA4 & CMP1_P
2/CMP
2_O
U
T
RES
E
T
/G
PI
O
A
7
GP
IO
B
3
/M
O
S
I/
TI
N3
/A
NA3
& ANB
3
/P
W
M
5
/CM
P
1
_O
UT
GPIOA3/PWM3/TXD/EXTAL
GPIOA2/PWM2
GPIOB0/SCLK/SCL/ANB13/PWM3/T1
GPIOA5/PWM5/FAULT2 or EXT_SYNC/TIN3
GPIOB4/T0/CLKO_0/MISO/SDA/RXD/ANA0 & ANB0
GPIOA6/FAULT0/ANA1 & ANB1/SCL/TXD/CLKO_1
GPIOB2/MISO/TIN2/ANA2 & ANB2/CMP0_OUT
T
D
O/
GPI
O
D1
/ANB
10/
T
0
/CMP
2_OUT
T
M
S/
GPI
O
D3
/ANB
11/
T
1
/CMP
1_OUT
T
D
I/
GP
IO
D0/A
NB12/
SS
/TI
N
2/CMP
0_OUT
GP
IO
A0
/PWM0
GP
IO
A1
/P
W
M
1
V
SS
V
DD
G
P
IO
F0
/X
T
A
L
GPIOA4/PWM4/SDA/FAULT1/TIN2
GPIOE0
GPIOE1/ANB9 & CMP0_P1
GPIOE2/ANB7 & CMP0_M1
GPIOC7/ANB5 & CMP1_M2
GPI
O
E
3
/A
NA10 & CMP2_
M
1
GP
IO
E5/
A
NA8 & CMP2_
P
1
GPI
O
E
4
/A
NA6 & CMP2_P
2
V
DD
Vss
GPIOE6
V
DD
GPIOE7/CMP1_M3
GP
IO
F
3
/CMP
0_P3
GP
IO
F2
/C
M
P
0
_
M
3
GP
IO
F
1
/CMP
1_P3
GP
IO
C3
/E
XT
_T
RIG
G
ER
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
13
14
15
16
17
18
19
20
21
22
23
24