Freescale Semiconductor Tower System Module S12G240 TWR-S12G240 TWR-S12G240 Datenbogen
Produktcode
TWR-S12G240
Analog-to-Digital Converter (ADC12B12CV2)
MC9S12G Family Reference Manual,
Rev.1.23
502
Freescale Semiconductor
14.3.2
Register Descriptions
This section describes in address order all the ADC12B12C registers and their individual bits.
14.3.2.1
ATD Control Register 0 (ATDCTL0)
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime, in special modes always write 0 to Reserved Bit 7.
Module Base + 0x0000
7
6
5
4
3
2
1
0
R
Reserved
0
0
0
WRAP3
WRAP2
WRAP1
WRAP0
W
Reset
0
0
0
0
1
1
1
1
= Unimplemented or Reserved
Figure 14-3. ATD Control Register 0 (ATDCTL0)
Table 14-1. ATDCTL0 Field Descriptions
Field
Description
3-0
WRAP[3-0]
Wrap Around Channel Select Bits — These bits determine the channel for wrap around when doing
multi-channel conversions. The coding is summarized in
multi-channel conversions. The coding is summarized in
Table 14-2. Multi-Channel Wrap Around Coding
WRAP3
WRAP2
WRAP1
WRAP0
Multiple Channel Conversions (MULT = 1)
Wraparound to AN0 after Converting
0
0
0
0
Reserved
1
0
0
0
1
AN1
0
0
1
0
AN2
0
0
1
1
AN3
0
1
0
0
AN4
0
1
0
1
AN5
0
1
1
0
AN6
0
1
1
1
AN7
1
0
0
0
AN8
1
0
0
1
AN9
1
0
1
0
AN10
1
0
1
1
AN11
1
1
0
0
AN11
1
1
0
1
AN11
1
1
1
0
AN11
1
1
1
1
AN11