Datenbogen (TWR-S12G240)InhaltsverzeichnisChapter 1 Device Overview MC9S12G-Family371.1 Introduction371.2 Features381.2.1 MC9S12G-Family Comparison381.2.2 Chip-Level Features401.3 Module Features401.3.1 S12 16-Bit Central Processor Unit (CPU)411.3.2 On-Chip Flash with ECC411.3.3 On-Chip SRAM411.3.4 Port Integration Module (PIM)411.3.5 Main External Oscillator (XOSCLCP)421.3.6 Internal RC Oscillator (IRC)421.3.7 Internal Phase-Locked Loop (IPLL)421.3.8 System Integrity Support431.3.9 Timer (TIM)431.3.10 Pulse Width Modulation Module (PWM)431.3.11 Controller Area Network Module (MSCAN)431.3.12 Serial Communication Interface Module (SCI)441.3.13 Serial Peripheral Interface Module (SPI)441.3.14 Analog-to-Digital Converter Module (ADC)441.3.15 Reference Voltage Attenuator (RVA)451.3.16 Digital-to-Analog Converter Module (DAC)451.3.17 Analog Comparator (ACMP)451.3.18 On-Chip Voltage Regulator (VREG)451.3.19 Background Debug (BDM)451.3.20 Debugger (DBG)451.4 Key Performance Parameters461.5 Block Diagram461.6 Family Memory Map471.6.1 Part ID Assignments521.7 Signal Description and Device Pinouts521.7.1 Pin Assignment Overview531.7.2 Detailed Signal Descriptions531.7.2.1 RESET - External Reset Signal531.7.2.2 TEST - Test Pin531.7.2.3 BKGD / MODC - Background Debug and Mode Pin541.7.2.4 EXTAL, XTAL - Oscillator Signal541.7.2.5 PAD[15:0] / KWAD[15:0] - Port AD Input Pins of ADC541.7.2.6 PA[7:0] - Port A I/O Signals541.7.2.7 PB[7:0] - Port B I/O Signals541.7.2.8 PC[7:0] - Port C I/O Signals541.7.2.9 PD[7:0] - Port D I/O Signals541.7.2.10 PE[1:0] - Port E I/O Signals541.7.2.11 PJ[7:0] / KWJ[7:0] - Port J I/O Signals551.7.2.12 PM[3:0] - Port M I/O Signals551.7.2.13 PP[7:0] / KWP[7:0] - Port P I/O Signals551.7.2.14 PS[7:0] - Port S I/O Signals551.7.2.15 PT[7:0] - Port TI/O Signals551.7.2.16 AN[15:0] - ADC Input Signals551.7.2.17 ACMP Signals551.7.2.18 DAC Signals561.7.2.19 SPI Signals561.7.2.20 SCI Signals561.7.2.21 CAN signals571.7.2.22 PWM[7:0] Signals571.7.2.23 Internal Clock outputs571.7.2.24 IOC[7:0] Signals571.7.2.25 IRQ581.7.2.26 XIRQ581.7.2.27 ETRIG[3:0]581.7.3 Power Supply Pins581.7.3.1 VDDX[3:1]/VDDX, VSSX[3:1]/VSSX- Power and Ground Pins for I/O Drivers581.7.3.2 VDDR - Power Pin for Internal Voltage Regulator581.7.3.3 VSS - Core Ground Pin581.7.3.4 VDDA, VSSA - Power Supply Pins for DAC,ACMP, RVA, ADC and Voltage Regulator591.7.3.5 VRH - Reference Voltage Input Pin591.7.3.6 Power and Ground Connection Summary591.8 Device Pinouts601.8.1 S12GN16 and S12GN32601.8.1.1 Pinout 20-Pin TSSOP601.8.1.2 Pinout 32-Pin LQFP621.8.1.3 Pinout 48-Pin LQFP/QFN641.8.2 S12GNA16 and S12GNA32671.8.2.1 Pinout 48-Pin LQFP/QFN671.8.3 S12GN48691.8.3.1 Pinout 32-Pin LQFP691.8.3.2 Pinout 48-Pin LQFP721.8.3.3 Pinout 64-Pin LQFP751.8.4 S12G48 and S12G64791.8.4.1 Pinout 32-Pin LQFP791.8.4.2 Pinout 48-Pin LQFP811.8.4.3 Pinout 64-Pin LQFP841.8.5 S12GA48 and S12GA64881.8.5.1 Pinout 48-Pin LQFP881.8.5.2 Pinout 64-Pin LQFP911.8.6 S12G96 and S12G128951.8.6.1 Pinout 48-Pin LQFP951.8.6.2 Pinout 64-Pin LQFP981.8.6.3 Pinout 100-Pin LQFP1021.8.7 S12GA96 and S12GA1281071.8.7.1 Pinout 48-Pin LQFP1071.8.7.2 Pinout 64-Pin LQFP1101.8.7.3 Pinout 100-Pin LQFP1141.8.8 S12G192 and S12G2401191.8.8.1 Pinout 48-Pin LQFP1191.8.8.2 Pinout 64-Pin LQFP1221.8.8.3 Pinout 100-Pin LQFP1261.8.9 S12GA192 and S12GA2401311.8.9.1 Pinout 48-Pin LQFP1311.8.9.2 Pinout 64-Pin LQFP1341.8.9.3 Pinout 100-Pin LQFP1381.8.9.4 Known Good Die Option (KGD)1431.9 System Clock Description1461.10 Modes of Operation1461.10.1 Chip Configuration Summary1461.10.1.1 Normal Single-Chip Mode1471.10.1.2 Special Single-Chip Mode1471.10.2 Low Power Operation1471.11 Security1471.12 Resets and Interrupts1471.12.1 Resets1471.12.2 Interrupt Vectors1481.12.3 Effects of Reset1501.12.3.1 Flash Configuration Reset Sequence Phase1501.12.3.2 Reset While Flash Command Active1501.12.3.3 I/O Pins1501.12.3.4 RAM1501.13 COP Configuration1501.14 Autonomous Clock (ACLK) Configuration1511.15 ADC External Trigger Input Connection1511.16 ADC Special Conversion Channels1511.17 ADC Result Reference1521.18 ADC VRH/VRL Signal Connection1521.19 BDM Clock Source Connectivity153Chapter 2 Port Integration Module (S12GPIMV1)1552.1 Introduction1552.1.1 Glossary1552.1.2 Overview1562.1.3 Features1562.1.4 Block Diagram1572.2 PIM Routing - External Signal Description1572.2.1 Package Code1582.2.2 Prioritization1582.2.3 Signals and Priorities1582.3 PIM Routing - Functional description1602.3.1 Pin BKGD1692.3.2 Pins PA7-01692.3.3 Pins PB7-01692.3.4 Pins PC7-01692.3.5 Pins PD7-01712.3.6 Pins PE1-01712.3.7 Pins PT7-01712.3.8 Pins PS7-01732.3.9 Pins PM3-01752.3.10 Pins PP7-01752.3.11 Pins PJ7-01772.3.12 Pins AD15-01782.4 PIM Ports - Memory Map and Register Definition1842.4.1 Memory Map1842.4.2 Register Map1872.4.2.1 Block Register Map (G1)1872.4.2.2 Block Register Map (G2)1922.4.2.3 Block Register Map (G3)1972.4.3 Register Descriptions2022.4.3.1 Port A Data Register (PORTA)2032.4.3.2 Port B Data Register (PORTB)2032.4.3.3 Port A Data Direction Register (DDRA)2042.4.3.4 Port B Data Direction Register (DDRB)2052.4.3.5 Port C Data Register (PORTC)2052.4.3.6 Port D Data Register (PORTD)2062.4.3.7 Port C Data Direction Register (DDRC)2072.4.3.8 Port D Data Direction Register (DDRD)2072.4.3.9 Port E Data Register (PORTE)2082.4.3.10 Port E Data Direction Register (DDRE)2082.4.3.11 Ports A, B, C, D, E, BKGD pin Pull Control Register (PUCR)2092.4.3.12 ECLK Control Register (ECLKCTL)2112.4.3.13 IRQ Control Register (IRQCR)2112.4.3.14 Reserved Register2122.4.3.15 Port T Data Register (PTT)2132.4.3.16 Port T Input Register (PTIT)2132.4.3.17 Port T Data Direction Register (DDRT)2142.4.3.18 Port T Pull Device Enable Register (PERT)2152.4.3.19 Port T Polarity Select Register (PPST)2162.4.3.20 Port S Data Register (PTS)2162.4.3.21 Port S Input Register (PTIS)2172.4.3.22 Port S Data Direction Register (DDRS)2172.4.3.23 Port S Pull Device Enable Register (PERS)2182.4.3.24 Port S Polarity Select Register (PPSS)2182.4.3.25 Port S Wired-Or Mode Register (WOMS)2192.4.3.26 Pin Routing Register 0 (PRR0)2192.4.3.27 Port M Data Register (PTM)2212.4.3.28 Port M Input Register (PTIM)2222.4.3.29 Port M Data Direction Register (DDRM)2222.4.3.30 Port M Pull Device Enable Register (PERM)2232.4.3.31 Port M Polarity Select Register (PPSM)2242.4.3.32 Port M Wired-Or Mode Register (WOMM)2242.4.3.33 Package Code Register (PKGCR)2252.4.3.34 Port P Data Register (PTP)2262.4.3.35 Port P Input Register (PTIP)2272.4.3.36 Port P Data Direction Register (DDRP)2282.4.3.37 Port P Pull Device Enable Register (PERP)2282.4.3.38 Port P Polarity Select Register (PPSP)2292.4.3.39 Port P Interrupt Enable Register (PIEP)2302.4.3.40 Port P Interrupt Flag Register (PIFP)2302.4.3.41 Reserved Registers2322.4.3.42 Port J Data Register (PTJ)2322.4.3.43 Port J Input Register (PTIJ)2332.4.3.44 Port J Data Direction Register (DDRJ)2332.4.3.45 Port J Pull Device Enable Register (PERJ)2342.4.3.46 Port J Polarity Select Register (PPSJ)2352.4.3.47 Port J Interrupt Enable Register (PIEJ)2352.4.3.48 Port J Interrupt Flag Register (PIFJ)2362.4.3.49 Port AD Data Register (PT0AD)2372.4.3.50 Port AD Data Register (PT1AD)2372.4.3.51 Port AD Input Register (PTI0AD)2382.4.3.52 Port AD Input Register (PTI1AD)2382.4.3.53 Port AD Data Direction Register (DDR0AD)2392.4.3.54 Port AD Data Direction Register (DDR1AD)2392.4.3.55 Reserved Register2402.4.3.56 Pin Routing Register 1 (PRR1)2402.4.3.57 Port AD Pull Enable Register (PER0AD)2412.4.3.58 Port AD Pull Enable Register (PER1AD)2422.4.3.59 Port AD Polarity Select Register (PPS0AD)2422.4.3.60 Port AD Polarity Select Register (PPS1AD)2432.4.3.61 Port AD Interrupt Enable Register (PIE0AD)2442.4.3.62 Port AD Interrupt Enable Register (PIE1AD)2442.4.3.63 Port AD Interrupt Flag Register (PIF0AD)2452.4.3.64 Port AD Interrupt Flag Register (PIF1AD)2462.5 PIM Ports - Functional Description2472.5.1 General2472.5.2 Registers2472.5.2.1 Data Register (PORTx, PTx)2472.5.2.2 Input Register (PTIx)2472.5.2.3 Data Direction Register (DDRx)2482.5.2.4 Pull Device Enable Register (PERx)2482.5.2.5 Pin Polarity Select Register (PPSx)2482.5.2.6 Wired-Or Mode Register (WOMx)2492.5.2.7 Interrupt Enable Register (PIEx)2492.5.2.8 Interrupt Flag Register (PIFx)2492.5.2.9 Pin Routing Register (PRRx)2492.5.2.10 Package Code Register (PKGCR)2492.5.3 Pin Configuration Summary2492.5.4 Interrupts2502.5.4.1 XIRQ, IRQ Interrupts2502.5.4.2 Pin Interrupts and Wakeup2512.6 Initialization/Application Information2522.6.1 Initialization2522.6.2 Port Data and Data Direction Register writes2522.6.3 Enabling IRQ edge-sensitive mode2522.6.4 ADC External Triggers ETRIG3-02522.6.5 Emulation of Smaller Packages253Chapter 3 5V Analog Comparator (ACMPV1)2553.1 Introduction2553.2 Features2553.3 Block Diagram2553.4 External Signals2563.5 Modes of Operation2563.6 Memory Map and Register Definition2573.6.1 Register Map2573.6.2 Register Descriptions2573.6.2.1 ACMP Control Register (ACMPC)2573.6.2.2 ACMP Status Register (ACMPS)2583.7 Functional Description259Chapter 4 Reference Voltage Attenuator (RVAV1)2614.1 Introduction2614.2 Features2614.3 Block Diagram2614.4 External Signals2624.5 Modes of Operation2624.6 Memory Map and Register Definition2634.6.1 Register Map2634.6.2 Register Descriptions2634.6.2.1 RVA Control Register (RVACTL)2634.7 Functional Description264Chapter 5 S12G Memory Map Controller (S12GMMCV1)2655.1 Introduction2655.1.1 Glossary2655.1.2 Overview2655.1.3 Features2665.1.4 Modes of Operation2665.1.4.1 Functional Modes2665.1.4.2 Security2665.1.5 Block Diagram2665.2 External Signal Description2675.3 Memory Map and Registers2675.3.1 Module Memory Map2675.3.2 Register Descriptions2685.3.2.1 Mode Register (MODE)2685.3.2.2 Direct Page Register (DIRECT)2695.3.2.3 MMC Control Register (MMCCTL1)2705.3.2.4 Program Page Index Register (PPAGE)2715.4 Functional Description2725.4.1 MCU Operating Modes2725.4.2 Memory Map Scheme2725.4.2.1 CPU and BDM Memory Map Scheme2725.4.3 Unimplemented and Reserved Address Ranges2765.4.4 Prioritization of Memory Accesses2775.4.5 Interrupts277Chapter 6 Interrupt Module (S12SINTV1)2796.1 Introduction2796.1.1 Glossary2796.1.2 Features2796.1.3 Modes of Operation2806.1.4 Block Diagram2806.2 External Signal Description2816.3 Memory Map and Register Definition2816.3.1 Register Descriptions2816.3.1.1 Interrupt Vector Base Register (IVBR)2816.4 Functional Description2826.4.1 S12S Exception Requests2826.4.2 Interrupt Prioritization2826.4.3 Reset Exception Requests2836.4.4 Exception Priority2836.5 Initialization/Application Information2846.5.1 Initialization2846.5.2 Interrupt Nesting2846.5.3 Wake Up from Stop or Wait Mode2846.5.3.1 CPU Wake Up from Stop or Wait Mode284Chapter 7 Background Debug Module (S12SBDMV1)2877.1 Introduction2877.1.1 Features2877.1.2 Modes of Operation2887.1.2.1 Regular Run Modes2887.1.2.2 Secure Mode Operation2887.1.2.3 Low-Power Modes2887.1.3 Block Diagram2897.2 External Signal Description2897.3 Memory Map and Register Definition2897.3.1 Module Memory Map2897.3.2 Register Descriptions2907.3.2.1 BDM Status Register (BDMSTS)2917.3.2.2 BDM Program Page Index Register (BDMPPR)2937.3.3 Family ID Assignment2947.4 Functional Description2947.4.1 Security2947.4.2 Enabling and Activating BDM2947.4.3 BDM Hardware Commands2957.4.4 Standard BDM Firmware Commands2967.4.5 BDM Command Structure2977.4.6 BDM Serial Interface2997.4.7 Serial Interface Hardware Handshake Protocol3027.4.8 Hardware Handshake Abort Procedure3047.4.9 SYNC - Request Timed Reference Pulse3077.4.10 Instruction Tracing3077.4.11 Serial Communication Time Out308Chapter 8 S12S Debug Module (S12SDBGV2)3118.1 Introduction3118.1.1 Glossary Of Terms3118.1.2 Overview3128.1.3 Features3128.1.4 Modes of Operation3138.1.5 Block Diagram3138.2 External Signal Description3148.3 Memory Map and Registers3148.3.1 Module Memory Map3148.3.2 Register Descriptions3158.3.2.1 Debug Control Register 1 (DBGC1)3158.3.2.2 Debug Status Register (DBGSR)3168.3.2.3 Debug Trace Control Register (DBGTCR)3178.3.2.4 Debug Control Register2 (DBGC2)3188.3.2.5 Debug Trace Buffer Register (DBGTBH:DBGTBL)3198.3.2.6 Debug Count Register (DBGCNT)3198.3.2.7 Debug State Control Registers3208.3.2.8 Comparator Register Descriptions3248.4 Functional Description3308.4.1 S12SDBG Operation3318.4.2 Comparator Modes3318.4.2.1 Single Address Comparator Match3328.4.2.2 Range Comparisons3348.4.3 Match Modes (Forced or Tagged)3358.4.3.1 Forced Match3358.4.3.2 Tagged Match3358.4.3.3 Immediate Trigger3368.4.3.4 Channel Priorities3368.4.4 State Sequence Control3368.4.4.1 Final State3378.4.5 Trace Buffer Operation3378.4.5.1 Trace Trigger Alignment3378.4.5.2 Trace Modes3388.4.5.3 Trace Buffer Organization (Normal, Loop1, Detail modes)3408.4.5.4 Trace Buffer Organization (Compressed Pure PC mode)3428.4.5.5 Reading Data from Trace Buffer3438.4.5.6 Trace Buffer Reset State3438.4.6 Tagging3448.4.7 Breakpoints3448.4.7.1 Breakpoints From Comparator Channels3448.4.7.2 Breakpoints Generated Via The TRIG Bit3458.4.7.3 Breakpoint Priorities3458.5 Application Information3468.5.1 State Machine scenarios3468.5.2 Scenario 13468.5.3 Scenario 23478.5.4 Scenario 33478.5.5 Scenario 43478.5.6 Scenario 53498.5.7 Scenario 63498.5.8 Scenario 73498.5.9 Scenario 83508.5.10 Scenario 93508.5.11 Scenario 10350Chapter 9 Security (S12XS9SECV2)3539.1 Introduction3539.1.1 Features3539.1.2 Modes of Operation3539.1.3 Securing the Microcontroller3549.1.4 Operation of the Secured Microcontroller3559.1.4.1 Normal Single Chip Mode (NS)3559.1.4.2 Special Single Chip Mode (SS)3559.1.5 Unsecuring the Microcontroller3569.1.5.1 Unsecuring the MCU Using the Backdoor Key Access3569.1.6 Reprogramming the Security Bits3569.1.7 Complete Memory Erase (Special Modes)357Chapter 10 S12 Clock, Reset and Power Management Unit (S12CPMU)35910.1 Introduction35910.1.1 Features35910.1.2 Modes of Operation36210.1.2.1 Run Mode36210.1.2.2 Wait Mode36210.1.2.3 Stop Mode36410.1.3 S12CPMU Block Diagram36510.2 Signal Description36710.2.1 RESET36710.2.2 EXTAL and XTAL36710.2.3 VDDR - Regulator Power Input Pin36710.2.4 VSS - Ground Pin36710.2.5 VDDA, VSSA - Regulator Reference Supply Pins36710.2.6 VDDX, VSSX- Pad Supply Pins36710.2.7 VDD - Internal Regulator Output Supply (Core Logic)36810.2.8 VDDF - Internal Regulator Output Supply (NVM Logic)36810.2.9 API_EXTCLK - API external clock output pin36810.3 Memory Map and Registers36910.3.1 Module Memory Map36910.3.2 Register Descriptions37110.3.2.1 S12CPMU Synthesizer Register (CPMUSYNR)37110.3.2.2 S12CPMU Reference Divider Register (CPMUREFDIV)37210.3.2.3 S12CPMU Post Divider Register (CPMUPOSTDIV)37310.3.2.4 S12CPMU Flags Register (CPMUFLG)37310.3.2.5 S12CPMU Interrupt Enable Register (CPMUINT)37510.3.2.6 S12CPMU Clock Select Register (CPMUCLKS)37610.3.2.7 S12CPMU PLL Control Register (CPMUPLL)37910.3.2.8 S12CPMU RTI Control Register (CPMURTI)38010.3.2.9 S12CPMU COP Control Register (CPMUCOP)38310.3.2.10 Reserved Register CPMUTEST038610.3.2.11 Reserved Register CPMUTEST138610.3.2.12 S12CPMU COP Timer Arm/Reset Register (CPMUARMCOP)38710.3.2.13 Low Voltage Control Register (CPMULVCTL)38810.3.2.14 Autonomous Periodical Interrupt Control Register (CPMUAPICTL)38910.3.2.15 Autonomous Clock Trimming Register (CPMUACLKTR)39110.3.2.16 Autonomous Periodical Interrupt Rate High and Low Register (CPMUAPIRH / CPMUAPIRL)39210.3.2.17 Reserved Register CPMUTEST339410.3.2.18 S12CPMU IRC1M Trim Registers (CPMUIRCTRIMH / CPMUIRCTRIML)39510.3.2.19 S12CPMU Oscillator Register (CPMUOSC)39910.3.2.20 S12CPMU Protection Register (CPMUPROT)40110.3.2.21 Reserved Register CPMUTEST240210.4 Functional Description40310.4.1 Phase Locked Loop with Internal Filter (PLL)40310.4.2 Startup from Reset40510.4.3 Stop Mode using PLLCLK as Bus Clock40510.4.4 Full Stop Mode using Oscillator Clock as Bus Clock40610.4.5 External Oscillator40710.4.5.1 Enabling the External Oscillator40710.4.6 System Clock Configurations40810.4.6.1 PLL Engaged Internal Mode (PEI)40810.4.6.2 PLL Engaged External Mode (PEE)40810.4.6.3 PLL Bypassed External Mode (PBE)40810.5 Resets40910.5.1 General40910.5.2 Description of Reset Operation40910.5.2.1 Clock Monitor Reset41010.5.2.2 Computer Operating Properly Watchdog (COP) Reset41110.5.3 Power-On Reset (POR)41210.5.4 Low-Voltage Reset (LVR)41210.6 Interrupts41210.6.1 Description of Interrupt Operation41210.6.1.1 Real Time Interrupt (RTI)41210.6.1.2 PLL Lock Interrupt41310.6.1.3 Oscillator Status Interrupt41310.6.1.4 Low-Voltage Interrupt (LVI)41310.6.1.5 Autonomous Periodical Interrupt (API)41310.7 Initialization/Application Information41410.7.1 General Initialization information41410.7.2 Application information for COP and API usage414Chapter 11 Analog-to-Digital Converter (ADC10B8CV2)41711.1 Introduction41711.1.1 Features41811.1.2 Modes of Operation41911.1.2.1 Conversion Modes41911.1.2.2 MCU Operating Modes41911.1.3 Block Diagram42011.2 Signal Description42111.2.1 Detailed Signal Descriptions42111.2.1.1 ANx (x = 7, 6, 5, 4, 3, 2, 1, 0)42111.2.1.2 ETRIG3, ETRIG2, ETRIG1, ETRIG042111.2.1.3 VRH, VRL42111.2.1.4 VDDA, VSSA42111.3 Memory Map and Register Definition42111.3.1 Module Memory Map42111.3.2 Register Descriptions42311.3.2.1 ATD Control Register 0 (ATDCTL0)42311.3.2.2 ATD Control Register 1 (ATDCTL1)42411.3.2.3 ATD Control Register 2 (ATDCTL2)42511.3.2.4 ATD Control Register 3 (ATDCTL3)42711.3.2.5 ATD Control Register 4 (ATDCTL4)42911.3.2.6 ATD Control Register 5 (ATDCTL5)43011.3.2.7 ATD Status Register 0 (ATDSTAT0)43211.3.2.8 ATD Compare Enable Register (ATDCMPE)43311.3.2.9 ATD Status Register 2 (ATDSTAT2)43411.3.2.10 ATD Input Enable Register (ATDDIEN)43511.3.2.11 ATD Compare Higher Than Register (ATDCMPHT)43511.3.2.12 ATD Conversion Result Registers (ATDDRn)43611.4 Functional Description43811.4.1 Analog Sub-Block43811.4.1.1 Sample and Hold Machine43811.4.1.2 Analog Input Multiplexer43811.4.1.3 Analog-to-Digital (A/D) Machine43811.4.2 Digital Sub-Block43811.4.2.1 External Trigger Input43811.4.2.2 General-Purpose Digital Port Operation43911.5 Resets44011.6 Interrupts440Chapter 12 Analog-to-Digital Converter (ADC12B8CV2)44112.1 Introduction44112.1.1 Features44212.1.2 Modes of Operation44312.1.2.1 Conversion Modes44312.1.2.2 MCU Operating Modes44312.1.3 Block Diagram44412.2 Signal Description44512.2.1 Detailed Signal Descriptions44512.2.1.1 ANx (x = 7, 6, 5, 4, 3, 2, 1, 0)44512.2.1.2 ETRIG3, ETRIG2, ETRIG1, ETRIG044512.2.1.3 VRH, VRL44512.2.1.4 VDDA, VSSA44512.3 Memory Map and Register Definition44512.3.1 Module Memory Map44512.3.2 Register Descriptions44712.3.2.1 ATD Control Register 0 (ATDCTL0)44712.3.2.2 ATD Control Register 1 (ATDCTL1)44812.3.2.3 ATD Control Register 2 (ATDCTL2)44912.3.2.4 ATD Control Register 3 (ATDCTL3)45112.3.2.5 ATD Control Register 4 (ATDCTL4)45312.3.2.6 ATD Control Register 5 (ATDCTL5)45412.3.2.7 ATD Status Register 0 (ATDSTAT0)45712.3.2.8 ATD Compare Enable Register (ATDCMPE)45812.3.2.9 ATD Status Register 2 (ATDSTAT2)45912.3.2.10 ATD Input Enable Register (ATDDIEN)46012.3.2.11 ATD Compare Higher Than Register (ATDCMPHT)46012.3.2.12 ATD Conversion Result Registers (ATDDRn)46112.4 Functional Description46312.4.1 Analog Sub-Block46312.4.1.1 Sample and Hold Machine46312.4.1.2 Analog Input Multiplexer46312.4.1.3 Analog-to-Digital (A/D) Machine46312.4.2 Digital Sub-Block46312.4.2.1 External Trigger Input46312.4.2.2 General-Purpose Digital Port Operation46412.5 Resets46512.6 Interrupts465Chapter 13 Analog-to-Digital Converter (ADC10B12CV2)46713.1 Introduction46813.1.1 Features46813.1.2 Modes of Operation46913.1.2.1 Conversion Modes46913.1.2.2 MCU Operating Modes46913.1.3 Block Diagram47013.2 Signal Description47113.2.1 Detailed Signal Descriptions47113.2.1.1 ANx (x = 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0)47113.2.1.2 ETRIG3, ETRIG2, ETRIG1, ETRIG047113.2.1.3 VRH, VRL47113.2.1.4 VDDA, VSSA47113.3 Memory Map and Register Definition47113.3.1 Module Memory Map47113.3.2 Register Descriptions47413.3.2.1 ATD Control Register 0 (ATDCTL0)47413.3.2.2 ATD Control Register 1 (ATDCTL1)47513.3.2.3 ATD Control Register 2 (ATDCTL2)47613.3.2.4 ATD Control Register 3 (ATDCTL3)47813.3.2.5 ATD Control Register 4 (ATDCTL4)48013.3.2.6 ATD Control Register 5 (ATDCTL5)48113.3.2.7 ATD Status Register 0 (ATDSTAT0)48313.3.2.8 ATD Compare Enable Register (ATDCMPE)48413.3.2.9 ATD Status Register 2 (ATDSTAT2)48513.3.2.10 ATD Input Enable Register (ATDDIEN)48613.3.2.11 ATD Compare Higher Than Register (ATDCMPHT)48613.3.2.12 ATD Conversion Result Registers (ATDDRn)48713.4 Functional Description48913.4.1 Analog Sub-Block48913.4.1.1 Sample and Hold Machine48913.4.1.2 Analog Input Multiplexer48913.4.1.3 Analog-to-Digital (A/D) Machine48913.4.2 Digital Sub-Block48913.4.2.1 External Trigger Input48913.4.2.2 General-Purpose Digital Port Operation49013.5 Resets49113.6 Interrupts491Chapter 14 Analog-to-Digital Converter (ADC12B12CV2)49314.1 Introduction49414.1.1 Features49414.1.2 Modes of Operation49514.1.2.1 Conversion Modes49514.1.2.2 MCU Operating Modes49514.1.3 Block Diagram49614.2 Signal Description49714.2.1 Detailed Signal Descriptions49714.2.1.1 ANx (x = 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0)49714.2.1.2 ETRIG3, ETRIG2, ETRIG1, ETRIG049714.2.1.3 VRH, VRL49714.2.1.4 VDDA, VSSA49714.3 Memory Map and Register Definition49714.3.1 Module Memory Map49714.3.2 Register Descriptions50014.3.2.1 ATD Control Register 0 (ATDCTL0)50014.3.2.2 ATD Control Register 1 (ATDCTL1)50114.3.2.3 ATD Control Register 2 (ATDCTL2)50214.3.2.4 ATD Control Register 3 (ATDCTL3)50414.3.2.5 ATD Control Register 4 (ATDCTL4)50614.3.2.6 ATD Control Register 5 (ATDCTL5)50714.3.2.7 ATD Status Register 0 (ATDSTAT0)51014.3.2.8 ATD Compare Enable Register (ATDCMPE)51114.3.2.9 ATD Status Register 2 (ATDSTAT2)51214.3.2.10 ATD Input Enable Register (ATDDIEN)51314.3.2.11 ATD Compare Higher Than Register (ATDCMPHT)51314.3.2.12 ATD Conversion Result Registers (ATDDRn)51414.4 Functional Description51614.4.1 Analog Sub-Block51614.4.1.1 Sample and Hold Machine51614.4.1.2 Analog Input Multiplexer51614.4.1.3 Analog-to-Digital (A/D) Machine51614.4.2 Digital Sub-Block51614.4.2.1 External Trigger Input51614.4.2.2 General-Purpose Digital Port Operation51714.5 Resets51814.6 Interrupts518Chapter 15 Analog-to-Digital Converter (ADC10B16CV2)51915.1 Introduction52015.1.1 Features52015.1.2 Modes of Operation52115.1.2.1 Conversion Modes52115.1.2.2 MCU Operating Modes52115.1.3 Block Diagram52215.2 Signal Description52315.2.1 Detailed Signal Descriptions52315.2.1.1 ANx (x = 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0)52315.2.1.2 ETRIG3, ETRIG2, ETRIG1, ETRIG052315.2.1.3 VRH, VRL52315.2.1.4 VDDA, VSSA52315.3 Memory Map and Register Definition52315.3.1 Module Memory Map52315.3.2 Register Descriptions52615.3.2.1 ATD Control Register 0 (ATDCTL0)52615.3.2.2 ATD Control Register 1 (ATDCTL1)52715.3.2.3 ATD Control Register 2 (ATDCTL2)52815.3.2.4 ATD Control Register 3 (ATDCTL3)53015.3.2.5 ATD Control Register 4 (ATDCTL4)53215.3.2.6 ATD Control Register 5 (ATDCTL5)53315.3.2.7 ATD Status Register 0 (ATDSTAT0)53515.3.2.8 ATD Compare Enable Register (ATDCMPE)53615.3.2.9 ATD Status Register 2 (ATDSTAT2)53715.3.2.10 ATD Input Enable Register (ATDDIEN)53815.3.2.11 ATD Compare Higher Than Register (ATDCMPHT)53815.3.2.12 ATD Conversion Result Registers (ATDDRn)53915.4 Functional Description54115.4.1 Analog Sub-Block54115.4.1.1 Sample and Hold Machine54115.4.1.2 Analog Input Multiplexer54115.4.1.3 Analog-to-Digital (A/D) Machine54115.4.2 Digital Sub-Block54115.4.2.1 External Trigger Input54115.4.2.2 General-Purpose Digital Port Operation54215.5 Resets54315.6 Interrupts543Chapter 16 Analog-to-Digital Converter (ADC12B16CV2)54516.1 Introduction54616.1.1 Features54616.1.2 Modes of Operation54716.1.2.1 Conversion Modes54716.1.2.2 MCU Operating Modes54716.1.3 Block Diagram54816.2 Signal Description54916.2.1 Detailed Signal Descriptions54916.2.1.1 ANx (x = 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0)54916.2.1.2 ETRIG3, ETRIG2, ETRIG1, ETRIG054916.2.1.3 VRH, VRL54916.2.1.4 VDDA, VSSA54916.3 Memory Map and Register Definition54916.3.1 Module Memory Map54916.3.2 Register Descriptions55216.3.2.1 ATD Control Register 0 (ATDCTL0)55216.3.2.2 ATD Control Register 1 (ATDCTL1)55316.3.2.3 ATD Control Register 2 (ATDCTL2)55416.3.2.4 ATD Control Register 3 (ATDCTL3)55616.3.2.5 ATD Control Register 4 (ATDCTL4)55816.3.2.6 ATD Control Register 5 (ATDCTL5)55916.3.2.7 ATD Status Register 0 (ATDSTAT0)56216.3.2.8 ATD Compare Enable Register (ATDCMPE)56316.3.2.9 ATD Status Register 2 (ATDSTAT2)56416.3.2.10 ATD Input Enable Register (ATDDIEN)56516.3.2.11 ATD Compare Higher Than Register (ATDCMPHT)56516.3.2.12 ATD Conversion Result Registers (ATDDRn)56616.4 Functional Description56816.4.1 Analog Sub-Block56816.4.1.1 Sample and Hold Machine56816.4.1.2 Analog Input Multiplexer56816.4.1.3 Analog-to-Digital (A/D) Machine56816.4.2 Digital Sub-Block56816.4.2.1 External Trigger Input56816.4.2.2 General-Purpose Digital Port Operation56916.5 Resets57016.6 Interrupts570Chapter 17 Digital Analog Converter (DAC_8B5V)57117.1 Revision History57117.2 Introduction57217.2.1 Features57217.2.2 Modes of Operation57217.2.3 Block Diagram57317.3 External Signal Description57317.3.1 DACU Output Pin57317.3.2 AMP Output Pin57317.3.3 AMPP Input Pin57317.3.4 AMPM Input Pin57417.4 Memory Map and Register Definition57417.4.1 Register Summary57417.4.2 Register Descriptions57417.4.2.1 Control Register (DACCTL)57517.4.2.2 Analog Output Voltage Level Register (DACVOL)57617.4.2.3 Reserved Register57617.5 Functional Description57617.5.1 Functional Overview57617.5.2 Mode “Off”57717.5.3 Mode “Operational Amplifier”57717.5.4 Mode “Unbuffered DAC”57817.5.5 Mode “Unbuffered DAC with Operational Amplifier”57817.5.6 Mode “Buffered DAC”57817.5.7 Analog output voltage calculation578Chapter 18 Freescale’s Scalable Controller Area Network (S12MSCANV3)58318.1 Introduction58318.1.1 Glossary58418.1.2 Block Diagram58418.1.3 Features58518.1.4 Modes of Operation58518.2 External Signal Description58518.2.1 RXCAN - CAN Receiver Input Pin58518.2.2 TXCAN - CAN Transmitter Output Pin58618.2.3 CAN System58618.3 Memory Map and Register Definition58618.3.1 Module Memory Map58618.3.2 Register Descriptions58818.3.2.1 MSCAN Control Register 0 (CANCTL0)58818.3.2.2 MSCAN Control Register 1 (CANCTL1)59018.3.2.3 MSCAN Bus Timing Register 0 (CANBTR0)59218.3.2.4 MSCAN Bus Timing Register 1 (CANBTR1)59318.3.2.5 MSCAN Receiver Flag Register (CANRFLG)59418.3.2.6 MSCAN Receiver Interrupt Enable Register (CANRIER)59618.3.2.7 MSCAN Transmitter Flag Register (CANTFLG)59718.3.2.8 MSCAN Transmitter Interrupt Enable Register (CANTIER)59818.3.2.9 MSCAN Transmitter Message Abort Request Register (CANTARQ)59918.3.2.10 MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)60018.3.2.11 MSCAN Transmit Buffer Selection Register (CANTBSEL)60018.3.2.12 MSCAN Identifier Acceptance Control Register (CANIDAC)60118.3.2.13 MSCAN Reserved Register60218.3.2.14 MSCAN Miscellaneous Register (CANMISC)60318.3.2.15 MSCAN Receive Error Counter (CANRXERR)60318.3.2.16 MSCAN Transmit Error Counter (CANTXERR)60418.3.2.17 MSCAN Identifier Acceptance Registers (CANIDAR0-7)60418.3.2.18 MSCAN Identifier Mask Registers (CANIDMR0-CANIDMR7)60518.3.3 Programmer’s Model of Message Storage60718.3.3.1 Identifier Registers (IDR0-IDR3)60918.3.3.2 Data Segment Registers (DSR0-7)61318.3.3.3 Data Length Register (DLR)61318.3.3.4 Transmit Buffer Priority Register (TBPR)61418.3.3.5 Time Stamp Register (TSRH-TSRL)61518.4 Functional Description61618.4.1 General61618.4.2 Message Storage61718.4.2.1 Message Transmit Background61718.4.2.2 Transmit Structures61818.4.2.3 Receive Structures61918.4.3 Identifier Acceptance Filter62018.4.3.1 Protocol Violation Protection62418.4.3.2 Clock System62418.4.4 Modes of Operation62618.4.4.1 Normal System Operating Modes62618.4.4.2 Special System Operating Modes62718.4.4.3 Emulation Modes62718.4.4.4 Listen-Only Mode62718.4.4.5 MSCAN Initialization Mode62718.4.5 Low-Power Options62818.4.5.1 Operation in Run Mode62918.4.5.2 Operation in Wait Mode62918.4.5.3 Operation in Stop Mode62918.4.5.4 MSCAN Normal Mode62918.4.5.5 MSCAN Sleep Mode63018.4.5.6 MSCAN Power Down Mode63118.4.5.7 Disabled Mode63218.4.5.8 Programmable Wake-Up Function63218.4.6 Reset Initialization63218.4.7 Interrupts63218.4.7.1 Description of Interrupt Operation63218.4.7.2 Transmit Interrupt63218.4.7.3 Receive Interrupt63318.4.7.4 Wake-Up Interrupt63318.4.7.5 Error Interrupt63318.4.7.6 Interrupt Acknowledge63318.5 Initialization/Application Information63418.5.1 MSCAN initialization63418.5.2 Bus-Off Recovery634Chapter 19 Pulse-Width Modulator (S12PWM8B8CV2)63519.1 Introduction63519.1.1 Features63519.1.2 Modes of Operation63519.1.3 Block Diagram63619.2 External Signal Description63619.2.1 PWM7 - PWM0 - PWM Channel 7 - 063619.3 Memory Map and Register Definition63719.3.1 Module Memory Map63719.3.2 Register Descriptions63719.3.2.1 PWM Enable Register (PWME)64019.3.2.2 PWM Polarity Register (PWMPOL)64119.3.2.3 PWM Clock Select Register (PWMCLK)64219.3.2.4 PWM Prescale Clock Select Register (PWMPRCLK)64319.3.2.5 PWM Center Align Enable Register (PWMCAE)64419.3.2.6 PWM Control Register (PWMCTL)64519.3.2.7 PWM Clock A/B Select Register (PWMCLKAB)64619.3.2.8 PWM Scale A Register (PWMSCLA)64819.3.2.9 PWM Scale B Register (PWMSCLB)64819.3.2.10 PWM Channel Counter Registers (PWMCNTx)64919.3.2.11 PWM Channel Period Registers (PWMPERx)64919.3.2.12 PWM Channel Duty Registers (PWMDTYx)65019.4 Functional Description65219.4.1 PWM Clock Select65219.4.1.1 Prescale65219.4.1.2 Clock Scale65219.4.1.3 Clock Select65419.4.2 PWM Channel Timers65519.4.2.1 PWM Enable65519.4.2.2 PWM Polarity65619.4.2.3 PWM Period and Duty65619.4.2.4 PWM Timer Counters65619.4.2.5 Left Aligned Outputs65719.4.2.6 Center Aligned Outputs65919.4.2.7 PWM 16-Bit Functions66019.4.2.8 PWM Boundary Cases66219.5 Resets66219.6 Interrupts663Chapter 20 Serial Communication Interface (S12SCIV5)66520.1 Introduction66520.1.1 Glossary66520.1.2 Features66620.1.3 Modes of Operation66620.1.4 Block Diagram66720.2 External Signal Description66720.2.1 TXD - Transmit Pin66720.2.2 RXD - Receive Pin66720.3 Memory Map and Register Definition66720.3.1 Module Memory Map and Register Definition66820.3.2 Register Descriptions66820.3.2.1 SCI Baud Rate Registers (SCIBDH, SCIBDL)66920.3.2.2 SCI Control Register 1 (SCICR1)67020.3.2.3 SCI Alternative Status Register 1 (SCIASR1)67220.3.2.4 SCI Alternative Control Register 1 (SCIACR1)67220.3.2.5 SCI Alternative Control Register 2 (SCIACR2)67320.3.2.6 SCI Control Register 2 (SCICR2)67420.3.2.7 SCI Status Register 1 (SCISR1)67520.3.2.8 SCI Status Register 2 (SCISR2)67720.3.2.9 SCI Data Registers (SCIDRH, SCIDRL)67820.4 Functional Description67920.4.1 Infrared Interface Submodule68020.4.1.1 Infrared Transmit Encoder68120.4.1.2 Infrared Receive Decoder68120.4.2 LIN Support68120.4.3 Data Format68120.4.4 Baud Rate Generation68320.4.5 Transmitter68420.4.5.1 Transmitter Character Length68420.4.5.2 Character Transmission68420.4.5.3 Break Characters68620.4.5.4 Idle Characters68720.4.5.5 LIN Transmit Collision Detection68820.4.6 Receiver68920.4.6.1 Receiver Character Length68920.4.6.2 Character Reception68920.4.6.3 Data Sampling69020.4.6.4 Framing Errors69420.4.6.5 Baud Rate Tolerance69420.4.6.6 Receiver Wakeup69620.4.7 Single-Wire Operation69720.4.8 Loop Operation69820.5 Initialization/Application Information69820.5.1 Reset Initialization69820.5.2 Modes of Operation69820.5.2.1 Run Mode69820.5.2.2 Wait Mode69820.5.2.3 Stop Mode69920.5.3 Interrupt Operation69920.5.3.1 Description of Interrupt Operation69920.5.4 Recovery from Wait Mode70120.5.5 Recovery from Stop Mode701Chapter 21 Serial Peripheral Interface (S12SPIV5)70321.1 Introduction70321.1.1 Glossary of Terms70321.1.2 Features70321.1.3 Modes of Operation70421.1.4 Block Diagram70421.2 External Signal Description70521.2.1 MOSI - Master Out/Slave In Pin70521.2.2 MISO - Master In/Slave Out Pin70621.2.3 SS - Slave Select Pin70621.2.4 SCK - Serial Clock Pin70621.3 Memory Map and Register Definition70621.3.1 Module Memory Map70621.3.2 Register Descriptions70721.3.2.1 SPI Control Register 1 (SPICR1)70721.3.2.2 SPI Control Register 2 (SPICR2)70821.3.2.3 SPI Baud Rate Register (SPIBR)71021.3.2.4 SPI Status Register (SPISR)71221.3.2.5 SPI Data Register (SPIDR = SPIDRH:SPIDRL)71421.4 Functional Description71521.4.1 Master Mode71621.4.2 Slave Mode71721.4.3 Transmission Formats71821.4.3.1 Clock Phase and Polarity Controls71921.4.3.2 CPHA = 0 Transfer Format71921.4.3.3 CPHA = 1 Transfer Format72121.4.4 SPI Baud Rate Generation72421.4.5 Special Features72521.4.5.1 SS Output72521.4.5.2 Bidirectional Mode (MOMI or SISO)72521.4.6 Error Conditions72621.4.6.1 Mode Fault Error72621.4.7 Low Power Mode Options72721.4.7.1 SPI in Run Mode72721.4.7.2 SPI in Wait Mode72721.4.7.3 SPI in Stop Mode72821.4.7.4 Reset72821.4.7.5 Interrupts728Chapter 22 Timer Module (TIM16B6CV3)73122.1 Introduction73122.1.1 Features73122.1.2 Modes of Operation73122.1.3 Block Diagrams73222.2 External Signal Description73322.2.1 IOC5 - IOC0 - Input Capture and Output Compare Channel 5-073322.3 Memory Map and Register Definition73322.3.1 Module Memory Map73322.3.2 Register Descriptions73322.3.2.1 Timer Input Capture/Output Compare Select (TIOS)73522.3.2.2 Timer Compare Force Register (CFORC)73522.3.2.3 Timer Count Register (TCNT)73622.3.2.4 Timer System Control Register 1 (TSCR1)73622.3.2.5 Timer Toggle On Overflow Register 1 (TTOV)73722.3.2.6 Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2)73822.3.2.7 Timer Control Register 3/Timer Control Register 4 (TCTL3 and TCTL4)73922.3.2.8 Timer Interrupt Enable Register (TIE)74022.3.2.9 Timer System Control Register 2 (TSCR2)74022.3.2.10 Main Timer Interrupt Flag 1 (TFLG1)74122.3.2.11 Main Timer Interrupt Flag 2 (TFLG2)74222.3.2.12 Timer Input Capture/Output Compare Registers High and Low 0- 5(TCxH and TCxL)74322.3.2.13 Output Compare Pin Disconnect Register(OCPD)74422.3.2.14 Precision Timer Prescaler Select Register (PTPSR)74422.4 Functional Description74522.4.1 Prescaler74622.4.2 Input Capture74722.4.3 Output Compare74722.4.3.1 OC Channel Initialization74722.5 Resets74822.6 Interrupts74822.6.1 Channel [5:0] Interrupt (C[5:0]F)74822.6.2 Timer Overflow Interrupt (TOF)748Chapter 23 Timer Module (TIM16B8CV3)74923.1 Introduction74923.1.1 Features74923.1.2 Modes of Operation75023.1.3 Block Diagrams75023.2 External Signal Description75323.2.1 IOC7 - Input Capture and Output Compare Channel 775323.2.2 IOC6 - IOC0 - Input Capture and Output Compare Channel 6-075323.3 Memory Map and Register Definition75323.3.1 Module Memory Map75323.3.2 Register Descriptions75423.3.2.1 Timer Input Capture/Output Compare Select (TIOS)75523.3.2.2 Timer Compare Force Register (CFORC)75623.3.2.3 Output Compare 7 Mask Register (OC7M)75623.3.2.4 Output Compare 7 Data Register (OC7D)75723.3.2.5 Timer Count Register (TCNT)75723.3.2.6 Timer System Control Register 1 (TSCR1)75823.3.2.7 Timer Toggle On Overflow Register 1 (TTOV)75923.3.2.8 Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2)76023.3.2.9 Timer Control Register 3/Timer Control Register 4 (TCTL3 and TCTL4)76123.3.2.10 Timer Interrupt Enable Register (TIE)76223.3.2.11 Timer System Control Register 2 (TSCR2)76323.3.2.12 Main Timer Interrupt Flag 1 (TFLG1)76423.3.2.13 Main Timer Interrupt Flag 2 (TFLG2)76423.3.2.14 Timer Input Capture/Output Compare Registers High and Low 0- 7(TCxH and TCxL)76523.3.2.15 16-Bit Pulse Accumulator Control Register (PACTL)76623.3.2.16 Pulse Accumulator Flag Register (PAFLG)76723.3.2.17 Pulse Accumulators Count Registers (PACNT)76823.3.2.18 Output Compare Pin Disconnect Register(OCPD)76923.3.2.19 Precision Timer Prescaler Select Register (PTPSR)76923.4 Functional Description77023.4.1 Prescaler77223.4.2 Input Capture77223.4.3 Output Compare77223.4.3.1 OC Channel Initialization77323.4.4 Pulse Accumulator77323.4.5 Event Counter Mode77423.4.6 Gated Time Accumulation Mode77423.5 Resets77423.6 Interrupts77423.6.1 Channel [7:0] Interrupt (C[7:0]F)77523.6.2 Pulse Accumulator Input Interrupt (PAOVI)77523.6.3 Pulse Accumulator Overflow Interrupt (PAOVF)77523.6.4 Timer Overflow Interrupt (TOF)775Chapter 24 16 KByte Flash Module (S12FTMRG16K1V1)77724.1 Introduction77724.1.1 Glossary77824.1.2 Features77824.1.2.1 P-Flash Features77824.1.2.2 EEPROM Features77924.1.2.3 Other Flash Module Features77924.1.3 Block Diagram77924.2 External Signal Description78024.3 Memory Map and Registers78124.3.1 Module Memory Map78124.3.2 Register Descriptions78424.3.2.1 Flash Clock Divider Register (FCLKDIV)78624.3.2.2 Flash Security Register (FSEC)78724.3.2.3 Flash CCOB Index Register (FCCOBIX)78924.3.2.4 Flash Reserved0 Register (FRSV0)78924.3.2.5 Flash Configuration Register (FCNFG)78924.3.2.6 Flash Error Configuration Register (FERCNFG)79024.3.2.7 Flash Status Register (FSTAT)79124.3.2.8 Flash Error Status Register (FERSTAT)79224.3.2.9 P-Flash Protection Register (FPROT)79324.3.2.10 EEPROM Protection Register (EEPROT)79524.3.2.11 Flash Common Command Object Register (FCCOB)79624.3.2.12 Flash Reserved1 Register (FRSV1)79724.3.2.13 Flash Reserved2 Register (FRSV2)79824.3.2.14 Flash Reserved3 Register (FRSV3)79824.3.2.15 Flash Reserved4 Register (FRSV4)79824.3.2.16 Flash Option Register (FOPT)79924.3.2.17 Flash Reserved5 Register (FRSV5)79924.3.2.18 Flash Reserved6 Register (FRSV6)79924.3.2.19 Flash Reserved7 Register (FRSV7)80024.4 Functional Description80124.4.1 Modes of Operation80124.4.2 IFR Version ID Word80124.4.3 Internal NVM resource (NVMRES)80124.4.4 Flash Command Operations80124.4.4.1 Writing the FCLKDIV Register80124.4.4.2 Command Write Sequence80224.4.4.3 Valid Flash Module Commands80424.4.4.4 P-Flash Commands80424.4.4.5 EEPROM Commands80524.4.5 Allowed Simultaneous P-Flash and EEPROM Operations80624.4.6 Flash Command Description80724.4.6.1 Erase Verify All Blocks Command80724.4.6.2 Erase Verify Block Command80824.4.6.3 Erase Verify P-Flash Section Command80824.4.6.4 Read Once Command80924.4.6.5 Program P-Flash Command81024.4.6.6 Program Once Command81124.4.6.7 Erase All Blocks Command81224.4.6.8 Erase Flash Block Command81224.4.6.9 Erase P-Flash Sector Command81324.4.6.10 Unsecure Flash Command81424.4.6.11 Verify Backdoor Access Key Command81524.4.6.12 Set User Margin Level Command81524.4.6.13 Set Field Margin Level Command81724.4.6.14 Erase Verify EEPROM Section Command81824.4.6.15 Program EEPROM Command81924.4.6.16 Erase EEPROM Sector Command82024.4.7 Interrupts82124.4.7.1 Description of Flash Interrupt Operation82124.4.8 Wait Mode82224.4.9 Stop Mode82224.5 Security82224.5.1 Unsecuring the MCU using Backdoor Key Access82224.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM82324.5.3 Mode and Security Effects on Flash Command Availability82424.6 Initialization824Chapter 25 32 KByte Flash Module (S12FTMRG32K1V1)82525.1 Introduction82525.1.1 Glossary82625.1.2 Features82625.1.2.1 P-Flash Features82625.1.2.2 EEPROM Features82725.1.2.3 Other Flash Module Features82725.1.3 Block Diagram82725.2 External Signal Description82825.3 Memory Map and Registers82925.3.1 Module Memory Map82925.3.2 Register Descriptions83225.3.2.1 Flash Clock Divider Register (FCLKDIV)83425.3.2.2 Flash Security Register (FSEC)83625.3.2.3 Flash CCOB Index Register (FCCOBIX)83725.3.2.4 Flash Reserved0 Register (FRSV0)83725.3.2.5 Flash Configuration Register (FCNFG)83825.3.2.6 Flash Error Configuration Register (FERCNFG)83825.3.2.7 Flash Status Register (FSTAT)83925.3.2.8 Flash Error Status Register (FERSTAT)84025.3.2.9 P-Flash Protection Register (FPROT)84125.3.2.10 EEPROM Protection Register (EEPROT)84525.3.2.11 Flash Common Command Object Register (FCCOB)84725.3.2.12 Flash Reserved1 Register (FRSV1)84825.3.2.13 Flash Reserved2 Register (FRSV2)84825.3.2.14 Flash Reserved3 Register (FRSV3)84825.3.2.15 Flash Reserved4 Register (FRSV4)84925.3.2.16 Flash Option Register (FOPT)84925.3.2.17 Flash Reserved5 Register (FRSV5)85025.3.2.18 Flash Reserved6 Register (FRSV6)85025.3.2.19 Flash Reserved7 Register (FRSV7)85025.4 Functional Description85125.4.1 Modes of Operation85125.4.2 IFR Version ID Word85125.4.3 Internal NVM resource (NVMRES)85225.4.4 Flash Command Operations85225.4.4.1 Writing the FCLKDIV Register85225.4.4.2 Command Write Sequence85225.4.4.3 Valid Flash Module Commands85525.4.4.4 P-Flash Commands85525.4.4.5 EEPROM Commands85625.4.5 Allowed Simultaneous P-Flash and EEPROM Operations85725.4.6 Flash Command Description85825.4.6.1 Erase Verify All Blocks Command85825.4.6.2 Erase Verify Block Command85925.4.6.3 Erase Verify P-Flash Section Command85925.4.6.4 Read Once Command86025.4.6.5 Program P-Flash Command86125.4.6.6 Program Once Command86225.4.6.7 Erase All Blocks Command86325.4.6.8 Erase Flash Block Command86325.4.6.9 Erase P-Flash Sector Command86425.4.6.10 Unsecure Flash Command86525.4.6.11 Verify Backdoor Access Key Command86525.4.6.12 Set User Margin Level Command86625.4.6.13 Set Field Margin Level Command86825.4.6.14 Erase Verify EEPROM Section Command86925.4.6.15 Program EEPROM Command87025.4.6.16 Erase EEPROM Sector Command87125.4.7 Interrupts87225.4.7.1 Description of Flash Interrupt Operation87225.4.8 Wait Mode87325.4.9 Stop Mode87325.5 Security87325.5.1 Unsecuring the MCU using Backdoor Key Access87325.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM87425.5.3 Mode and Security Effects on Flash Command Availability87525.6 Initialization875Chapter 26 48 KByte Flash Module (S12FTMRG48K1V1)87726.1 Introduction87726.1.1 Glossary87826.1.2 Features87826.1.2.1 P-Flash Features87826.1.2.2 EEPROM Features87926.1.2.3 Other Flash Module Features87926.1.3 Block Diagram88026.2 External Signal Description88026.3 Memory Map and Registers88126.3.1 Module Memory Map88126.3.2 Register Descriptions88526.3.2.1 Flash Clock Divider Register (FCLKDIV)88726.3.2.2 Flash Security Register (FSEC)88926.3.2.3 Flash CCOB Index Register (FCCOBIX)89026.3.2.4 Flash Reserved0 Register (FRSV0)89026.3.2.5 Flash Configuration Register (FCNFG)89126.3.2.6 Flash Error Configuration Register (FERCNFG)89126.3.2.7 Flash Status Register (FSTAT)89226.3.2.8 Flash Error Status Register (FERSTAT)89326.3.2.9 P-Flash Protection Register (FPROT)89426.3.2.10 EEPROM Protection Register (EEPROT)89826.3.2.11 Flash Common Command Object Register (FCCOB)90026.3.2.12 Flash Reserved1 Register (FRSV1)90126.3.2.13 Flash Reserved2 Register (FRSV2)90126.3.2.14 Flash Reserved3 Register (FRSV3)90126.3.2.15 Flash Reserved4 Register (FRSV4)90226.3.2.16 Flash Option Register (FOPT)90226.3.2.17 Flash Reserved5 Register (FRSV5)90326.3.2.18 Flash Reserved6 Register (FRSV6)90326.3.2.19 Flash Reserved7 Register (FRSV7)90326.4 Functional Description90426.4.1 Modes of Operation90426.4.2 IFR Version ID Word90426.4.3 Internal NVM resource (NVMRES)90526.4.4 Flash Command Operations90526.4.4.1 Writing the FCLKDIV Register90526.4.4.2 Command Write Sequence90526.4.4.3 Valid Flash Module Commands90826.4.4.4 P-Flash Commands90826.4.4.5 EEPROM Commands90926.4.5 Allowed Simultaneous P-Flash and EEPROM Operations91026.4.6 Flash Command Description91126.4.6.1 Erase Verify All Blocks Command91126.4.6.2 Erase Verify Block Command91226.4.6.3 Erase Verify P-Flash Section Command91226.4.6.4 Read Once Command91326.4.6.5 Program P-Flash Command91426.4.6.6 Program Once Command91526.4.6.7 Erase All Blocks Command91626.4.6.8 Erase Flash Block Command91626.4.6.9 Erase P-Flash Sector Command91726.4.6.10 Unsecure Flash Command91826.4.6.11 Verify Backdoor Access Key Command91826.4.6.12 Set User Margin Level Command91926.4.6.13 Set Field Margin Level Command92126.4.6.14 Erase Verify EEPROM Section Command92226.4.6.15 Program EEPROM Command92326.4.6.16 Erase EEPROM Sector Command92426.4.7 Interrupts92526.4.7.1 Description of Flash Interrupt Operation92526.4.8 Wait Mode92626.4.9 Stop Mode92626.5 Security92626.5.1 Unsecuring the MCU using Backdoor Key Access92626.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM92726.5.3 Mode and Security Effects on Flash Command Availability92826.6 Initialization928Chapter 27 64 KByte Flash Module (S12FTMRG64K1V1)92927.1 Introduction92927.1.1 Glossary93027.1.2 Features93027.1.2.1 P-Flash Features93027.1.2.2 EEPROM Features93127.1.2.3 Other Flash Module Features93127.1.3 Block Diagram93127.2 External Signal Description93227.3 Memory Map and Registers93327.3.1 Module Memory Map93327.3.2 Register Descriptions93627.3.2.1 Flash Clock Divider Register (FCLKDIV)93827.3.2.2 Flash Security Register (FSEC)94027.3.2.3 Flash CCOB Index Register (FCCOBIX)94127.3.2.4 Flash Reserved0 Register (FRSV0)94127.3.2.5 Flash Configuration Register (FCNFG)94227.3.2.6 Flash Error Configuration Register (FERCNFG)94227.3.2.7 Flash Status Register (FSTAT)94327.3.2.8 Flash Error Status Register (FERSTAT)94427.3.2.9 P-Flash Protection Register (FPROT)94527.3.2.10 EEPROM Protection Register (EEPROT)94927.3.2.11 Flash Common Command Object Register (FCCOB)95127.3.2.12 Flash Reserved1 Register (FRSV1)95227.3.2.13 Flash Reserved2 Register (FRSV2)95227.3.2.14 Flash Reserved3 Register (FRSV3)95227.3.2.15 Flash Reserved4 Register (FRSV4)95327.3.2.16 Flash Option Register (FOPT)95327.3.2.17 Flash Reserved5 Register (FRSV5)95427.3.2.18 Flash Reserved6 Register (FRSV6)95427.3.2.19 Flash Reserved7 Register (FRSV7)95427.4 Functional Description95527.4.1 Modes of Operation95527.4.2 IFR Version ID Word95527.4.3 Internal NVM resource (NVMRES)95627.4.4 Flash Command Operations95627.4.4.1 Writing the FCLKDIV Register95627.4.4.2 Command Write Sequence95627.4.4.3 Valid Flash Module Commands95927.4.4.4 P-Flash Commands95927.4.4.5 EEPROM Commands96027.4.5 Allowed Simultaneous P-Flash and EEPROM Operations96127.4.6 Flash Command Description96227.4.6.1 Erase Verify All Blocks Command96227.4.6.2 Erase Verify Block Command96327.4.6.3 Erase Verify P-Flash Section Command96327.4.6.4 Read Once Command96427.4.6.5 Program P-Flash Command96527.4.6.6 Program Once Command96627.4.6.7 Erase All Blocks Command96727.4.6.8 Erase Flash Block Command96727.4.6.9 Erase P-Flash Sector Command96827.4.6.10 Unsecure Flash Command96927.4.6.11 Verify Backdoor Access Key Command96927.4.6.12 Set User Margin Level Command97027.4.6.13 Set Field Margin Level Command97227.4.6.14 Erase Verify EEPROM Section Command97327.4.6.15 Program EEPROM Command97427.4.6.16 Erase EEPROM Sector Command97527.4.7 Interrupts97627.4.7.1 Description of Flash Interrupt Operation97627.4.8 Wait Mode97727.4.9 Stop Mode97727.5 Security97727.5.1 Unsecuring the MCU using Backdoor Key Access97727.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM97827.5.3 Mode and Security Effects on Flash Command Availability97927.6 Initialization979Chapter 28 96 KByte Flash Module (S12FTMRG96K1V1)98128.1 Introduction98128.1.1 Glossary98228.1.2 Features98228.1.2.1 P-Flash Features98228.1.2.2 EEPROM Features98328.1.2.3 Other Flash Module Features98328.1.3 Block Diagram98328.2 External Signal Description98428.3 Memory Map and Registers98528.3.1 Module Memory Map98528.3.2 Register Descriptions98828.3.2.1 Flash Clock Divider Register (FCLKDIV)99028.3.2.2 Flash Security Register (FSEC)99228.3.2.3 Flash CCOB Index Register (FCCOBIX)99328.3.2.4 Flash Reserved0 Register (FRSV0)99328.3.2.5 Flash Configuration Register (FCNFG)99428.3.2.6 Flash Error Configuration Register (FERCNFG)99428.3.2.7 Flash Status Register (FSTAT)99528.3.2.8 Flash Error Status Register (FERSTAT)99628.3.2.9 P-Flash Protection Register (FPROT)99728.3.2.10 EEPROM Protection Register (EEPROT)100128.3.2.11 Flash Common Command Object Register (FCCOB)100328.3.2.12 Flash Reserved1 Register (FRSV1)100428.3.2.13 Flash Reserved2 Register (FRSV2)100428.3.2.14 Flash Reserved3 Register (FRSV3)100428.3.2.15 Flash Reserved4 Register (FRSV4)100528.3.2.16 Flash Option Register (FOPT)100528.3.2.17 Flash Reserved5 Register (FRSV5)100628.3.2.18 Flash Reserved6 Register (FRSV6)100628.3.2.19 Flash Reserved7 Register (FRSV7)100628.4 Functional Description100728.4.1 Modes of Operation100728.4.2 IFR Version ID Word100728.4.3 Internal NVM resource (NVMRES)100828.4.4 Flash Command Operations100828.4.4.1 Writing the FCLKDIV Register100828.4.4.2 Command Write Sequence100828.4.4.3 Valid Flash Module Commands101128.4.4.4 P-Flash Commands101128.4.4.5 EEPROM Commands101228.4.5 Allowed Simultaneous P-Flash and EEPROM Operations101328.4.6 Flash Command Description101428.4.6.1 Erase Verify All Blocks Command101428.4.6.2 Erase Verify Block Command101528.4.6.3 Erase Verify P-Flash Section Command101628.4.6.4 Read Once Command101628.4.6.5 Program P-Flash Command101728.4.6.6 Program Once Command101828.4.6.7 Erase All Blocks Command101928.4.6.8 Erase Flash Block Command102028.4.6.9 Erase P-Flash Sector Command102028.4.6.10 Unsecure Flash Command102128.4.6.11 Verify Backdoor Access Key Command102228.4.6.12 Set User Margin Level Command102228.4.6.13 Set Field Margin Level Command102428.4.6.14 Erase Verify EEPROM Section Command102528.4.6.15 Program EEPROM Command102628.4.6.16 Erase EEPROM Sector Command102728.4.7 Interrupts102828.4.7.1 Description of Flash Interrupt Operation102828.4.8 Wait Mode102928.4.9 Stop Mode102928.5 Security102928.5.1 Unsecuring the MCU using Backdoor Key Access102928.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM103028.5.3 Mode and Security Effects on Flash Command Availability103128.6 Initialization1031Chapter 29 128 KByte Flash Module (S12FTMRG128K1V1)103329.1 Introduction103329.1.1 Glossary103429.1.2 Features103429.1.2.1 P-Flash Features103429.1.2.2 EEPROM Features103529.1.2.3 Other Flash Module Features103529.1.3 Block Diagram103529.2 External Signal Description103629.3 Memory Map and Registers103729.3.1 Module Memory Map103729.3.2 Register Descriptions104129.3.2.1 Flash Clock Divider Register (FCLKDIV)104229.3.2.2 Flash Security Register (FSEC)104429.3.2.3 Flash CCOB Index Register (FCCOBIX)104529.3.2.4 Flash Reserved0 Register (FRSV0)104629.3.2.5 Flash Configuration Register (FCNFG)104629.3.2.6 Flash Error Configuration Register (FERCNFG)104729.3.2.7 Flash Status Register (FSTAT)104829.3.2.8 Flash Error Status Register (FERSTAT)104929.3.2.9 P-Flash Protection Register (FPROT)105029.3.2.10 EEPROM Protection Register (DFPROT)105329.3.2.11 Flash Common Command Object Register (FCCOB)105529.3.2.12 Flash Reserved1 Register (FRSV1)105629.3.2.13 Flash Reserved2 Register (FRSV2)105629.3.2.14 Flash Reserved3 Register (FRSV3)105629.3.2.15 Flash Reserved4 Register (FRSV4)105729.3.2.16 Flash Option Register (FOPT)105729.3.2.17 Flash Reserved5 Register (FRSV5)105829.3.2.18 Flash Reserved6 Register (FRSV6)105829.3.2.19 Flash Reserved7 Register (FRSV7)105829.4 Functional Description105929.4.1 Modes of Operation105929.4.2 IFR Version ID Word105929.4.3 Internal NVM resource (NVMRES)106029.4.4 Flash Command Operations106029.4.4.1 Writing the FCLKDIV Register106029.4.4.2 Command Write Sequence106029.4.4.3 Valid Flash Module Commands106329.4.4.4 P-Flash Commands106329.4.4.5 EEPROM Commands106429.4.5 Allowed Simultaneous P-Flash and EEPROM Operations106529.4.6 Flash Command Description106629.4.6.1 Erase Verify All Blocks Command106629.4.6.2 Erase Verify Block Command106729.4.6.3 Erase Verify P-Flash Section Command106729.4.6.4 Read Once Command106829.4.6.5 Program P-Flash Command106929.4.6.6 Program Once Command107029.4.6.7 Erase All Blocks Command107129.4.6.8 Erase Flash Block Command107129.4.6.9 Erase P-Flash Sector Command107229.4.6.10 Unsecure Flash Command107329.4.6.11 Verify Backdoor Access Key Command107329.4.6.12 Set User Margin Level Command107429.4.6.13 Set Field Margin Level Command107629.4.6.14 Erase Verify EEPROM Section Command107729.4.6.15 Program EEPROM Command107829.4.6.16 Erase EEPROM Sector Command107929.4.7 Interrupts108029.4.7.1 Description of Flash Interrupt Operation108029.4.8 Wait Mode108129.4.9 Stop Mode108129.5 Security108129.5.1 Unsecuring the MCU using Backdoor Key Access108129.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM108229.5.3 Mode and Security Effects on Flash Command Availability108329.6 Initialization1083Chapter 30 192 KByte Flash Module (S12FTMRG192K2V1)108530.1 Introduction108530.1.1 Glossary108630.1.2 Features108630.1.2.1 P-Flash Features108630.1.2.2 EEPROM Features108730.1.2.3 Other Flash Module Features108730.1.3 Block Diagram108730.2 External Signal Description108830.3 Memory Map and Registers108930.3.1 Module Memory Map108930.3.2 Register Descriptions109330.3.2.1 Flash Clock Divider Register (FCLKDIV)109430.3.2.2 Flash Security Register (FSEC)109630.3.2.3 Flash CCOB Index Register (FCCOBIX)109730.3.2.4 Flash Reserved0 Register (FRSV0)109830.3.2.5 Flash Configuration Register (FCNFG)109830.3.2.6 Flash Error Configuration Register (FERCNFG)109930.3.2.7 Flash Status Register (FSTAT)110030.3.2.8 Flash Error Status Register (FERSTAT)110130.3.2.9 P-Flash Protection Register (FPROT)110230.3.2.10 EEPROM Protection Register (EEPROT)110530.3.2.11 Flash Common Command Object Register (FCCOB)110730.3.2.12 Flash Reserved1 Register (FRSV1)110830.3.2.13 Flash Reserved2 Register (FRSV2)110830.3.2.14 Flash Reserved3 Register (FRSV3)110830.3.2.15 Flash Reserved4 Register (FRSV4)110930.3.2.16 Flash Option Register (FOPT)110930.3.2.17 Flash Reserved5 Register (FRSV5)111030.3.2.18 Flash Reserved6 Register (FRSV6)111030.3.2.19 Flash Reserved7 Register (FRSV7)111030.4 Functional Description111130.4.1 Modes of Operation111130.4.2 IFR Version ID Word111130.4.3 Internal NVM resource (NVMRES)111230.4.4 Flash Command Operations111230.4.4.1 Writing the FCLKDIV Register111230.4.4.2 Command Write Sequence111230.4.4.3 Valid Flash Module Commands111530.4.4.4 P-Flash Commands111530.4.4.5 EEPROM Commands111630.4.5 Allowed Simultaneous P-Flash and EEPROM Operations111730.4.6 Flash Command Description111830.4.6.1 Erase Verify All Blocks Command111830.4.6.2 Erase Verify Block Command111930.4.6.3 Erase Verify P-Flash Section Command111930.4.6.4 Read Once Command112030.4.6.5 Program P-Flash Command112130.4.6.6 Program Once Command112230.4.6.7 Erase All Blocks Command112330.4.6.8 Erase Flash Block Command112330.4.6.9 Erase P-Flash Sector Command112430.4.6.10 Unsecure Flash Command112530.4.6.11 Verify Backdoor Access Key Command112530.4.6.12 Set User Margin Level Command112630.4.6.13 Set Field Margin Level Command112730.4.6.14 Erase Verify EEPROM Section Command112930.4.6.15 Program EEPROM Command113030.4.6.16 Erase EEPROM Sector Command113030.4.7 Interrupts113130.4.7.1 Description of Flash Interrupt Operation113230.4.8 Wait Mode113230.4.9 Stop Mode113230.5 Security113330.5.1 Unsecuring the MCU using Backdoor Key Access113330.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM113430.5.3 Mode and Security Effects on Flash Command Availability113430.6 Initialization1134Chapter 31 240 KByte Flash Module (S12FTMRG240K2V1)113731.1 Introduction113731.1.1 Glossary113831.1.2 Features113831.1.2.1 P-Flash Features113831.1.2.2 EEPROM Features113931.1.2.3 Other Flash Module Features113931.1.3 Block Diagram113931.2 External Signal Description114031.3 Memory Map and Registers114131.3.1 Module Memory Map114131.3.2 Register Descriptions114531.3.2.1 Flash Clock Divider Register (FCLKDIV)114631.3.2.2 Flash Security Register (FSEC)114831.3.2.3 Flash CCOB Index Register (FCCOBIX)114931.3.2.4 Flash Reserved0 Register (FRSV0)115031.3.2.5 Flash Configuration Register (FCNFG)115031.3.2.6 Flash Error Configuration Register (FERCNFG)115131.3.2.7 Flash Status Register (FSTAT)115231.3.2.8 Flash Error Status Register (FERSTAT)115331.3.2.9 P-Flash Protection Register (FPROT)115431.3.2.10 EEPROM Protection Register (EEPROT)115731.3.2.11 Flash Common Command Object Register (FCCOB)115931.3.2.12 Flash Reserved1 Register (FRSV1)116031.3.2.13 Flash Reserved2 Register (FRSV2)116031.3.2.14 Flash Reserved3 Register (FRSV3)116031.3.2.15 Flash Reserved4 Register (FRSV4)116131.3.2.16 Flash Option Register (FOPT)116131.3.2.17 Flash Reserved5 Register (FRSV5)116231.3.2.18 Flash Reserved6 Register (FRSV6)116231.3.2.19 Flash Reserved7 Register (FRSV7)116231.4 Functional Description116331.4.1 Modes of Operation116331.4.2 IFR Version ID Word116331.4.3 Internal NVM resource (NVMRES)116431.4.4 Flash Command Operations116431.4.4.1 Writing the FCLKDIV Register116431.4.4.2 Command Write Sequence116431.4.4.3 Valid Flash Module Commands116731.4.4.4 P-Flash Commands116731.4.4.5 EEPROM Commands116831.4.5 Allowed Simultaneous P-Flash and EEPROM Operations116931.4.6 Flash Command Description117031.4.6.1 Erase Verify All Blocks Command117031.4.6.2 Erase Verify Block Command117131.4.6.3 Erase Verify P-Flash Section Command117131.4.6.4 Read Once Command117231.4.6.5 Program P-Flash Command117331.4.6.6 Program Once Command117431.4.6.7 Erase All Blocks Command117531.4.6.8 Erase Flash Block Command117531.4.6.9 Erase P-Flash Sector Command117631.4.6.10 Unsecure Flash Command117731.4.6.11 Verify Backdoor Access Key Command117731.4.6.12 Set User Margin Level Command117831.4.6.13 Set Field Margin Level Command117931.4.6.14 Erase Verify EEPROM Section Command118131.4.6.15 Program EEPROM Command118231.4.6.16 Erase EEPROM Sector Command118231.4.7 Interrupts118331.4.7.1 Description of Flash Interrupt Operation118431.4.8 Wait Mode118431.4.9 Stop Mode118431.5 Security118531.5.1 Unsecuring the MCU using Backdoor Key Access118531.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM118631.5.3 Mode and Security Effects on Flash Command Availability118631.6 Initialization1186Appendix A Electrical Characteristics1189A.1 General1190A.1.1 Parameter Classification1190A.1.2 Power Supply1190A.1.3 Pins1191A.1.3.1 I/O Pins1191A.1.3.2 Analog Reference1191A.1.3.3 Oscillator1191A.1.3.4 TEST1191A.1.4 Current Injection1191A.1.5 Absolute Maximum Ratings1192A.1.6 ESD Protection and Latch-up Immunity1192A.1.7 Operating Conditions1193A.1.8 Power Dissipation and Thermal Characteristics1195A.2 I/O Characteristics1199A.3 Supply Currents1203A.3.1 Measurement Conditions1203A.4 ADC Characteristics1208A.4.1 ADC Operating Characteristics1208A.4.2 Factors Influencing Accuracy1209A.4.2.1 Differential Reference Voltage1209A.4.2.2 Port AD Output Drivers Switching1209A.4.2.3 Source Resistance1209A.4.2.4 Source Capacitance1210A.4.2.5 Current Injection1210A.4.3 ADC Accuracy1210A.4.3.1 ADC Accuracy Definitions1211A.4.3.2 ADC Analog Input Parasitics1220A.4.4 ADC Temperature Sensor1220A.5 ACMP Characteristics1220A.6 DAC Characteristics1222A.7 NVM1223A.7.1 Timing Parameters1223A.7.1.1 Erase Verify All Blocks (Blank Check) (FCMD=0x01)1224A.7.1.2 Erase Verify Block (Blank Check) (FCMD=0x02)1224A.7.1.3 Erase Verify P-Flash Section (FCMD=0x03)1225A.7.1.4 Read Once (FCMD=0x04)1225A.7.1.5 Program P-Flash (FCMD=0x06)1226A.7.1.6 Program Once (FCMD=0x07)1226A.7.1.7 Erase All Blocks (FCMD=0x08)1226A.7.1.8 Erase P-Flash Block (FCMD=0x09)1227A.7.1.9 Erase P-Flash Sector (FCMD=0x0A)1227A.7.1.10 Unsecure Flash (FCMD=0x0B)1227A.7.1.11 Verify Backdoor Access Key (FCMD=0x0C)1228A.7.1.12 Set User Margin Level (FCMD=0x0D)1228A.7.1.13 Set Field Margin Level (FCMD=0x0E)1228A.7.1.14 Erase Verify EEPROM Section (FCMD=0x10)1228A.7.1.15 Program EEPROM (FCMD=0x11)1229A.7.1.16 Erase EEPROM Sector (FCMD=0x12)1229A.7.2 NVM Reliability Parameters1231A.8 Phase Locked Loop1232A.8.1 Jitter Definitions1232A.8.2 Electrical Characteristics for the PLL1234A.9 Electrical Characteristics for the IRC1M1234A.10 Electrical Characteristics for the Oscillator (XOSCLCP)1236A.11 Reset Characteristics1237A.12 Electrical Specification for Voltage Regulator1238A.13 Chip Power-up and Voltage Drops1240A.14 MSCAN1240A.15 SPI Timing1241A.15.1 Master Mode1241A.15.2 Slave Mode1243A.16 ADC Conversion Result Reference1245Appendix B Detailed Register Address Map1247B.1 Detailed Register Map1247Appendix C Ordering and Shipping Information1267C.1 Ordering Information1267Appendix D Package and Die Information1269D.1 100 LQFP Mechanical Dimensions1270D.2 64 LQFP Mechanical Dimensions1273D.3 48 LQFP Mechanical Dimensions1276D.4 48 QFN Mechanical Dimensions1278D.5 32 LQFP Mechanical Dimensions1281D.6 20 TSSOP Mechanical Dimensions1284D.7 KGD Information1287Größe: 8,06 MBSeiten: 1292Language: EnglishHandbuch öffnen