Freescale Semiconductor Tower System Module S12G240 TWR-S12G240 TWR-S12G240 Datenbogen

Freescale Semiconductor

697

As the receiver samples an incoming frame, it re-synchronizes the RT clock on any valid falling edge
within the frame. Re synchronization within frames will correct a misalignment between transmitter bit
times and receiver bit times.

 shows how much a slow received frame can be misaligned without causing a noise error or

a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data
samples at RT8, RT9, and RT10.

Let’s take RTr as receiver RT clock and RTt as transmitter RT clock.

For an 8-bit data character, it takes the receiver 9 bit times x 16 RTr cycles +7 RTr cycles = 151 RTr cycles
to start data sampling of the stop bit.

With the misaligned character shown in

, the receiver counts 151 RTr cycles at the point when

the count of the transmitting device is 9 bit times x 16 RTt cycles = 144 RTt cycles.

The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit data
character with no errors is:

((151 – 144) / 151) x 100 = 4.63%

For a 9-bit data character, it takes the receiver 10 bit times x 16 RTr cycles + 7 RTr cycles = 167 RTr cycles
to start data sampling of the stop bit.

With the misaligned character shown in

, the receiver counts 167 RTr cycles at the point when

the count of the transmitting device is 10 bit times x 16 RTt cycles = 160 RTt cycles.

The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit
character with no errors is:

((167 – 160) / 167) X 100 = 4.19%

 shows how much a fast received frame can be misaligned. The fast stop bit ends at RT10

instead of RT16 but is still sampled at RT8, RT9, and RT10.

MSB

Stop

RT

1

RT

2

RT

3

RT

4

RT

5

RT

6

RT

7

RT

8

RT

9

R

T10

R

T11

R

T12

R

T13

R

T14

R

T15

R

T16

Data

Samples

Receiver

RT Clock