Freescale Semiconductor MSC8156 Evaluation Module MSC8156EVM MSC8156EVM Benutzerhandbuch
Produktcode
MSC8156EVM
MSC8156 Reference Manual, Rev. 2
19-26
Freescale
Semiconductor
TDM Interface
19.2.6.3 Threshold Pointers and Interrupts
The receive data buffers share two threshold levels. The TDM notifies the SC3850 core each time
it fills the receive buffer up to a threshold level. An example use of thresholds is the
implementation of double buffering with the first threshold in the middle of a buffer and the
second at the last eight bytes of the buffer.
it fills the receive buffer up to a threshold level. An example use of thresholds is the
implementation of double buffering with the first threshold in the middle of a buffer and the
second at the last eight bytes of the buffer.
When the TDM receiver fills the receive buffer through the system interface to an offset defined
by the first threshold, which is the TDMxRDBFT[RDBFT] field (see page 19-58), the
TDMxRER[RFTE] bit is set. If the TDMxRIER[RFTEE] bit is also set, a first threshold interrupt
is generated. The interrupt can be generated as pulse or level, as determined by the
TDMxRIR[RFTL] bit. If the interrupt is level, the ISR should clear the TDMxRER[RFTE] bit by
writing a 1 to it. If the interrupt is pulse, then there is no need to clear the status bit. When the
interrupt is asserted in the EPIC, then the SC3850 core can read all the receive buffers from their
beginning up to the byte to which the first threshold (RDBFT) points. Meanwhile, the TDM
keeps writing new data to the second part of the buffer.
by the first threshold, which is the TDMxRDBFT[RDBFT] field (see page 19-58), the
TDMxRER[RFTE] bit is set. If the TDMxRIER[RFTEE] bit is also set, a first threshold interrupt
is generated. The interrupt can be generated as pulse or level, as determined by the
TDMxRIR[RFTL] bit. If the interrupt is level, the ISR should clear the TDMxRER[RFTE] bit by
writing a 1 to it. If the interrupt is pulse, then there is no need to clear the status bit. When the
interrupt is asserted in the EPIC, then the SC3850 core can read all the receive buffers from their
beginning up to the byte to which the first threshold (RDBFT) points. Meanwhile, the TDM
keeps writing new data to the second part of the buffer.
When the TDM receiver fills the receive buffer through the system interface up to an offset
defined by the second threshold, which is the TDMxRDBST[RDBST] field (see page 19-60), the
TDMxRER[RSTE] bit is set. If the TDMxRIER[RSEEE] bit is also set, a second threshold
interrupt is generated. The second threshold interrupt can generate as pulse or level, as
determined by the TDMxRIR[RSTL] bit. If the interrupt is level, the ISR should clear the
TDMxRER[RSTE] bit by writing a 1 to it. If the interrupt is pulse, there is no need to clear the
status bit. When the interrupt is asserted in the EPIC, then the SC3850 core can read all the
receive buffers up to the byte to which the second threshold (TDMxRDBST[RDBST]) points.
Meanwhile, the TDM keeps writing new data to the first part of the buffer.
defined by the second threshold, which is the TDMxRDBST[RDBST] field (see page 19-60), the
TDMxRER[RSTE] bit is set. If the TDMxRIER[RSEEE] bit is also set, a second threshold
interrupt is generated. The second threshold interrupt can generate as pulse or level, as
determined by the TDMxRIR[RSTL] bit. If the interrupt is level, the ISR should clear the
TDMxRER[RSTE] bit by writing a 1 to it. If the interrupt is pulse, there is no need to clear the
status bit. When the interrupt is asserted in the EPIC, then the SC3850 core can read all the
receive buffers up to the byte to which the second threshold (TDMxRDBST[RDBST]) points.
Meanwhile, the TDM keeps writing new data to the first part of the buffer.
The transmit data buffers also share two threshold levels. The TDM notifies the SC3850 core
each time it reads from the transmit buffer to a threshold level. When the TDM transmitter reads
the transmit buffer through the system interface to an offset defined by the first threshold, which
is the TDMxTDBFT[TDBFT] field, the TDMxTER[TFTE] bit is set. If the TDMxTIER[TFTEE]
bit is also set, a first threshold interrupt is generated. The interrupt can generate as pulse or level,
as determined by the TDMxTIR[TFTL] bit. If the interrupt is level, then the ISR should clear the
TDMxTER[TFTE] bit by writing a 1 to it. If the interrupt is pulse, there is no need to clear the
status bit. When the interrupt is asserted in the EPIC, then the SC3850 core can fill all the
transmit buffers from their beginning up to the byte to which the first threshold (TDBFT) points.
Meanwhile, the TDM continues reading new data from the second part of the buffer.
each time it reads from the transmit buffer to a threshold level. When the TDM transmitter reads
the transmit buffer through the system interface to an offset defined by the first threshold, which
is the TDMxTDBFT[TDBFT] field, the TDMxTER[TFTE] bit is set. If the TDMxTIER[TFTEE]
bit is also set, a first threshold interrupt is generated. The interrupt can generate as pulse or level,
as determined by the TDMxTIR[TFTL] bit. If the interrupt is level, then the ISR should clear the
TDMxTER[TFTE] bit by writing a 1 to it. If the interrupt is pulse, there is no need to clear the
status bit. When the interrupt is asserted in the EPIC, then the SC3850 core can fill all the
transmit buffers from their beginning up to the byte to which the first threshold (TDBFT) points.
Meanwhile, the TDM continues reading new data from the second part of the buffer.
When the TDM transmitter reads the transmit buffer through the system interface up to an offset
defined by the second threshold, which is the TDMxTDBST[TDBST] field, the
TDMxTER[TSTE] bit is set. If the TDMxTEIR[TSTEE] bit is also set, a second threshold
interrupt is generated. The second threshold interrupt can generate as pulse or level, as
determined by the TDMxTIR[TSTL] bit. If the interrupt is level, the ISR should clear the
TDMxTER[TSTE] bit by writing a 1 to it. If the interrupt is pulse, then there is no need to clear
defined by the second threshold, which is the TDMxTDBST[TDBST] field, the
TDMxTER[TSTE] bit is set. If the TDMxTEIR[TSTEE] bit is also set, a second threshold
interrupt is generated. The second threshold interrupt can generate as pulse or level, as
determined by the TDMxTIR[TSTL] bit. If the interrupt is level, the ISR should clear the
TDMxTER[TSTE] bit by writing a 1 to it. If the interrupt is pulse, then there is no need to clear