Freescale Semiconductor MSC8156 Evaluation Module MSC8156EVM MSC8156EVM Benutzerhandbuch
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MSC8156EVM
Device-Level Timers
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
21-5
21.1.4 Timer Operating Modes
The timer operates in two modes:
Count the CLASS clock/2 or external events via the timer input using the primary clock.
Count the CLASS clock/2 or external events via the timer input using the primary clock
Count the CLASS clock/2 or external events via the timer input using the primary clock
while a second input signal, the secondary clock, is asserted, thus timing the width of the
secondary clock signal.
secondary clock signal.
Each timer can be configured in the following ways:
to count the rising, falling, or both edges of the selected input pin.
to decode and count quadrature encoded input signals.
to count up and down using dual inputs in a count with direction format.
program the timer terminal count value (modulo).
program the value loaded into the timer after it reaches its terminal count.
program the timer to count repeatedly or to stop after completing one count cycle.
program the timer to count to a programmed value (using the compare functionality)
to decode and count quadrature encoded input signals.
to count up and down using dual inputs in a count with direction format.
program the timer terminal count value (modulo).
program the value loaded into the timer after it reaches its terminal count.
program the timer to count repeatedly or to stop after completing one count cycle.
program the timer to count to a programmed value (using the compare functionality)
and then immediately reinitialize or to count through the compare value until the count
rolls over to zero.
rolls over to zero.
The counting modes define the different modes for clocking the timers. The count mode is
selected in the TMRxCTL[CM] field (page 21-17). If a timer is programmed to count to a
specific value and then stop, the TMRCTL[CM] bit is cleared when the count terminates.
Table 21-3 summarizes the counting modes.
selected in the TMRxCTL[CM] field (page 21-17). If a timer is programmed to count to a
specific value and then stop, the TMRCTL[CM] bit is cleared when the count terminates.
Table 21-3 summarizes the counting modes.
Table 21-3. Summary of Timer Counting Modes
Counting Mode
CM Bits
Description
Primary Clock
Secondary
Clock
Disabled
000
Timer not active.
—
—
Count
001
Counts the rising edges of the selected clock source
(falling edges if TxSCTL[IPS] is set).
This mode is useful for generating periodic interrupts
for timing purposes or for counting external events.
(falling edges if TxSCTL[IPS] is set).
This mode is useful for generating periodic interrupts
for timing purposes or for counting external events.
Clock* —
Dual-Edge Count
010
Counts both edges of a timer Input signal.
This mode is useful for counting the changes in the
external environment. When this mode is selected,
TMRxCTL[PCS] must not be set to any value between
1000 and 1111; that is, it must not set to the input
clock or any scaled version of the input clock.
This mode is useful for counting the changes in the
external environment. When this mode is selected,
TMRxCTL[PCS] must not be set to any value between
1000 and 1111; that is, it must not set to the input
clock or any scaled version of the input clock.
Clock —