Freescale Semiconductor MSC8156 Evaluation Module MSC8156EVM MSC8156EVM Benutzerhandbuch
Produktcode
MSC8156EVM
MSC8156 Reference Manual, Rev. 2
21-6
Freescale
Semiconductor
Timers
Figure 21-2. Quadrature Incremental Position Encoder
Gated Count
011
Counts primary clock edges while the secondary input
is high (low if TxSCTL[IPS] is set). This mode is used
to time the duration of external events when the
primary clock is set to the input clock and the
secondary input is set to use one of the timer input
signals. It can also be used to count the number of
external events that occur on one of the timer input
signals, set as the primary clock, while a second timer
input signal, connected to the secondary Input signal,
is asserted.
is high (low if TxSCTL[IPS] is set). This mode is used
to time the duration of external events when the
primary clock is set to the input clock and the
secondary input is set to use one of the timer input
signals. It can also be used to count the number of
external events that occur on one of the timer input
signals, set as the primary clock, while a second timer
input signal, connected to the secondary Input signal,
is asserted.
Clock
Gate*
Quadrature
Count
Count
100
Counts using quadrature encoded signals.
The quadrature signals are square waves, 90 degrees
out of phase. The decoding of quadrature signal
provides both count and direction information. A timing
diagram illustrating the basic operation of a quadrature
incremental position encoder is provided in Figure
21-2.
The quadrature signals are square waves, 90 degrees
out of phase. The decoding of quadrature signal
provides both count and direction information. A timing
diagram illustrating the basic operation of a quadrature
incremental position encoder is provided in Figure
21-2.
Quadrature
signal
signal
Quadrature
signal
signal
Signed Count
101
Counts the primary clock source while a secondary
input provides the count direction (up or down) for
each recognized count.
input provides the count direction (up or down) for
each recognized count.
Clock to count
Count direction
Triggered Count
110
Counts the primary clock source only after a rising
edge is detected on the secondary input (falling edge if
TxSCTL[IPS] is set). The counting continues until a
compare event occurs or another positive input
transition is detected. If a second input transition
occurs before a terminal count is reached, counting
stops. Subsequent odd-numbered edges of the
secondary input restart the counting, and even
numbered edges stop counting. This process
continues until a compare event occurs.
edge is detected on the secondary input (falling edge if
TxSCTL[IPS] is set). The counting continues until a
compare event occurs or another positive input
transition is detected. If a second input transition
occurs before a terminal count is reached, counting
stops. Subsequent odd-numbered edges of the
secondary input restart the counting, and even
numbered edges stop counting. This process
continues until a compare event occurs.
Clock to count
Enable/disable
timer*
timer*
Cascade Count
111
Cascades multiple timers. Cascade mode is used for
creating timers larger than 16-bits. Up to four timers
may be cascaded together to create a 64-bit wide
timer. The Cascaded Timer mode is synchronous. See
Section 21.1.4.2.
creating timers larger than 16-bits. Up to four timers
may be cascaded together to create a 64-bit wide
timer. The Cascaded Timer mode is synchronous. See
Section 21.1.4.2.
Clock to count
Triggers timer
Note:
* This input can be inverted by the TxSCTL[IPS] bit.
Table 21-3. Summary of Timer Counting Modes
Counting Mode
CM Bits
Description
Primary Clock
Secondary
Clock
-1
-1
-1
-1
-1
-1
-1
PHASEA
COUNT
PHASEB
UP/DOWN
+1
+1
+1
+1
+1
+1
+1
+1