Freescale Semiconductor MSC8156 Evaluation Module MSC8156EVM MSC8156EVM Benutzerhandbuch

Freescale Semiconductor

 

25-3

To access the JTAG registers, shift the appropriate command into the JTAG instruction register 
and then shift the required value into the register. See Section 25.1.3 for a discussion of the 
JTAG instructions. Figure 25-1 shows the MSC8156 JTAG 5-bit instruction register and the 
following test registers: 

„ Boundary Scan Register (BSR). Regarding the length of the BSR, The boundary scan bit 

definitions vary according to the specific chip implementation of the MSC8156 and are 
described by the BSDL file on the product website

„ 1-bit Bypass Register
„ 32-bit Identification Register (ID)
„ 32 

× 32-bit General-Purpose Register Bank (GSBI) 

„ Test port access register

Table 25-1 lists the test access port (TAP) signals.

Figure 25-1.  Test Logic Block Diagram

Table 25-1.  TAP Signals

TCK

A test clock input to synchronize the test logic.

TMS 

A test mode select input (with an internal pull-up resistor) that is sampled on the rising edge of TCK to 
sequence the TAP controller state machine.

TDI 

A test data input (with an internal pull-up resistor) that is sampled on the rising edge of TCK.

8-Bit Instruction Register

TDO

TDI

TMS

TCK

TAP Controller

Boundary Scan Register

Bypass Register

Identification Register

8

M
U
X

General-Purpose Register

u

l
t
i

p

l

e

x

Parallel-Input Register

Instruction Apply and Decode

OCE Module Logic

M

e

r

TRST