Freescale Semiconductor MSC8156 Evaluation Module MSC8156EVM MSC8156EVM Benutzerhandbuch

Freescale Semiconductor

 

26-9

Each BD (regardless of its type) includes a [WRAP] bit. This bit tells MAPLE-B how to update 
the M<pe>BR(H/L)PAxP[BDR_RD_PTR] upon job completion. If the [WRAP] bit is not set 
then M<pe>BR(H/L)PAxP[BDR_RD_PTR] is increment with the BD size, that is, the next BD 
address is the current BD address plus the BD size. If the [WRAP] bit is set, then MAPLE-B 
updates the M<pe>BDR(H/L)PAxP[BDR_RD_PTR] with the value of 
M<pe>BR(H/L)PAxP[BDR_BA], that is, it expects to find the next BD at the base address of the 
current BD ring. 

The host must ensure that the last BD in its ring has the WRAP bit set. A state of one 
active BDR with single circular BD ([WRAP] bit is set) is forbidden for any of the 
PEs. Such a state may result in an unknown state of the MAPLE-B.

BD handshake with external masters uses the [OWNER] bit. Each BD (regardless of its type) 
includes an [OWNER] bit. If the [OWNER] bit of the BD is set, MAPLE-B starts executing this 
BD. On completion, it clears the [OWNER] bit and increments the 
M<pe>BR(H/L)PAxP[BDR_RD_PTR] as described above. If the [OWNER] bit is not set 
MAPLE-B continues to the next BD ring according to its arbitration scheme.

If no jobs are found in any of the BD-rings, or all of the accelerators are busy, the MAPLE-B 
hibernates and does not seek for new jobs. It wakes up due to one of the following reasons:

„ Internal counter time-out. For power consideration, the MAPLE-B implements an internal 

dynamic time-out counter that is activated internally and wakes the internal engine 
periodically to scan for new BDs.

„ A host accessing the PCR, as described in Section 26.4.3.1, PSIF Command Register 

„ Internal events from one of the PEs, such as job complete.

When a new BD job is found and the required accelerator is idle, the MAPLE-B proceeds with 
the BD execution. For details on job execution, refer to the specific accelerator used.

„ Section 26.3.1.4, Turbo/Viterbi Decoding Flow, on page 26-11

.

„ Section 26.3.2.2, FFT/iFFT/DFT/iDFT Operation, on page 26-80

„ Section 26.3.2.3, CRC Operation, on page 26-107

When a job is completed, the MAPLE-B clears the [OWNER] field, and if specified in the 
accelerator-specific BD, initiates an interrupt to the host. The 
M<pe>BDR(H/L)PBxP[INT_TRGT] field is used to define the target of this interrupt, with up to 
16 different target interrupts possible. If the M<pe>BRHPBxP[EXT_MST] is set to SoC external 
master, the MAPLE-B initiates a door-bell interrupt via the serial RapidIO port (see Section 
26.3.3.3, External Masters Support Using Serial RapidIO Doorbell for details).

Figure 26-2 illustrates the BD rings data structure and the mechanism of one PE in the PSIF 
DRAM of the MAPLE-B.