Freescale Semiconductor MSC8156 Evaluation Module MSC8156EVM MSC8156EVM Benutzerhandbuch
Produktcode
MSC8156EVM
MSC8156 Reference Manual, Rev. 2
26-148
Freescale
Semiconductor
Multi Accelerator Platform Engine, Baseband (MAPLE-B)
26.4.2.1.16
MAPLE CRCPE BD Ring High Priority A <x> Parameter
(MCRCBRHPAxP)
(MCRCBRHPAxP)
These parameters, along with MCRCBRHPBxP, describe the attributes of a High-Priority
CRCPE BD ring. There are 8 such parameters, one for each possible High-Priority CRCPE BD
ring.
CRCPE BD ring. There are 8 such parameters, one for each possible High-Priority CRCPE BD
ring.
EXT_MST
9–8
External Master
Describes if the Ring owner can receive any of the
MAPLE-B regular interrupt lines, and a regular
interrupt (one out of 16) is generated if the
[INT_EN] bit in the BD is set; or if the ring owner is
connected to the SoC via Serial RapidIO port and a
Serial RapidIO door-bell interrupt is generated if the
[INT_EN] bit in the BD is set. For more details see
Section 26.3.3.3, External Masters Support Using
Serial RapidIO Doorbell.
Describes if the Ring owner can receive any of the
MAPLE-B regular interrupt lines, and a regular
interrupt (one out of 16) is generated if the
[INT_EN] bit in the BD is set; or if the ring owner is
connected to the SoC via Serial RapidIO port and a
Serial RapidIO door-bell interrupt is generated if the
[INT_EN] bit in the BD is set. For more details see
Section 26.3.3.3, External Masters Support Using
Serial RapidIO Doorbell.
0b00 The master of this ring can receive any of the
MAPLE-B regular interrupts, therefore a
regular interrupt is generated according to
MDFBRLPBxP[INT_TRGT].
regular interrupt is generated according to
MDFBRLPBxP[INT_TRGT].
0b01 The master of this ring is external (connected
via Serial RapidIO port), therefore a Serial
RapidIO door-bell interrupt is generated using
MDFBRLPBxP[HOST_ID] (Section 26.3.3.3,
External Masters Support Using Serial
RapidIO Doorbell).
RapidIO door-bell interrupt is generated using
MDFBRLPBxP[HOST_ID] (Section 26.3.3.3,
External Masters Support Using Serial
RapidIO Doorbell).
0b10 Reserved.
0b11 Reserved.
0b11 Reserved.
INT_TRGT
7–4
Target Interrupt
Defines which regular interrupt is to be asserted
due to task completion in this BD ring. This field is
valid only if MDFBRLPBxP[EXT_MST] equals
0b00.
Defines which regular interrupt is to be asserted
due to task completion in this BD ring. This field is
valid only if MDFBRLPBxP[EXT_MST] equals
0b00.
0000 IRQ0
0001 IRQ1
...
1111 IRQ15
0001 IRQ1
...
1111 IRQ15
—
3–1
Reserved
VLD
0
Valid Bit
Describe if the current BD ring is valid. The
MAPLE-B uses this bit to determine the BD Ring
validation, therefore any change in any of the BD
Ring parameters must be done while the VLD bit is
cleared.
Describe if the current BD ring is valid. The
MAPLE-B uses this bit to determine the BD Ring
validation, therefore any change in any of the BD
Ring parameters must be done while the VLD bit is
cleared.
0
BD ring is not valid.
1
BD ring is valid.
Offset 0x00000200 (MCRCBRHPA0P)
offset x*0x8
range x = 0...7
range x = 0...7
Access: User read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
BDR_BA[13:8]
W
Initial
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
BDR_RD_PTR[13:5]
W
Initial
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 26-57. MAPLE CRCPE BD Ring High Priority A <x> Parameter
Table 26-82. MAPLE DFTPE BD Ring Low Priority B <x> Parameter Fields Description
Field
Description
Settings