Freescale Semiconductor MSC8156 Evaluation Module MSC8156EVM MSC8156EVM Benutzerhandbuch
Produktcode
MSC8156EVM
MSC8156 Reference Manual, Rev. 2
26-150
Freescale
Semiconductor
Multi Accelerator Platform Engine, Baseband (MAPLE-B)
Table 26-84. MAPLE CRCPE BD Ring High Priority B <x> Parameter Fields Description
Name
Description
Settings
HOST_ID
31–16
16 bits of Host ID
For Serial RapidIO door-bell support for an external
(to SoC) master connected to the SoC by the Serial
RapidIO port and owner of this ring. This field is valid
only if MDFBRHPBxP[EXT_MST] equals 01.
For Serial RapidIO door-bell support for an external
(to SoC) master connected to the SoC by the Serial
RapidIO port and owner of this ring. This field is valid
only if MDFBRHPBxP[EXT_MST] equals 01.
P_TR_IF
15–12
Port Target Interface
Determines which RapidIO port to use for this
doorbell. This field is used by the MAPLE-B for the
ODDATR[TGINT] field in the Serial RapidIO
Doorbell controller.
Determines which RapidIO port to use for this
doorbell. This field is used by the MAPLE-B for the
ODDATR[TGINT] field in the Serial RapidIO
Doorbell controller.
—
11–10
Reserved
EXT_MST
9–8
External Master
Describes whether the Ring owner can receive any
of the MAPLE-B regular interrupt lines, and a regular
interrupt (one out of 16) is generated if the [INT_EN]
bit in the BD is set; or if the ring owner is connected
to the SoC via Serial RapidIO port and a Serial
RapidIO door-bell interrupt is generated if the
[INT_EN] bit in the BD is set. For more details see
Section 26.3.3.3, External Masters Support
Using Serial RapidIO Doorbell.
Describes whether the Ring owner can receive any
of the MAPLE-B regular interrupt lines, and a regular
interrupt (one out of 16) is generated if the [INT_EN]
bit in the BD is set; or if the ring owner is connected
to the SoC via Serial RapidIO port and a Serial
RapidIO door-bell interrupt is generated if the
[INT_EN] bit in the BD is set. For more details see
Section 26.3.3.3, External Masters Support
Using Serial RapidIO Doorbell.
”
00
The master of this ring can receive any of the
MAPLE-B regular interrupts, therefore a
regular interrupt is generated according to
MCRCBRHPBxP[INT_TRGT].
MAPLE-B regular interrupts, therefore a
regular interrupt is generated according to
MCRCBRHPBxP[INT_TRGT].
01
The master of this ring is external (connected
via Serial RapidIO port), therefore a Serial
RapidIO door-bell interrupt is generated
(Section 26.3.3.3, External Masters
Support Using Serial RapidIO Doorbell
via Serial RapidIO port), therefore a Serial
RapidIO door-bell interrupt is generated
(Section 26.3.3.3, External Masters
Support Using Serial RapidIO Doorbell
).
10
Reserved.
11
Reserved
INT_TRGT
7–4
Target Interrupt
Defines which regular interrupt is to be asserted due
to task completion in this BD ring. This field is valid
only if MCRCBRHPBxP[EXT_MST] equals 00.
Defines which regular interrupt is to be asserted due
to task completion in this BD ring. This field is valid
only if MCRCBRHPBxP[EXT_MST] equals 00.
0000 IRQ0
0001 IRQ1
...
1111 IRQ15
0001 IRQ1
...
1111 IRQ15
—
3–1
Reserved
VLD
0
Valid Bit
Describes if the current BD ring is valid. The
MAPLE-B uses this bit to determine the BD Ring
validation, therefore any change in any of the BD
Ring parameters must be done while the VLD bit is
cleared.
0 BD ring is not valid.
1 BD ring is valid.
Describes if the current BD ring is valid. The
MAPLE-B uses this bit to determine the BD Ring
validation, therefore any change in any of the BD
Ring parameters must be done while the VLD bit is
cleared.
0 BD ring is not valid.
1 BD ring is valid.