Freescale Semiconductor MSC8156 Evaluation Module MSC8156EVM MSC8156EVM Benutzerhandbuch
Produktcode
MSC8156EVM
MSC8156 Reference Manual, Rev. 2
8-22
Freescale
Semiconductor
General Configuration Registers
8.2.13
General Control Register 5 (GCR5)
GCR5 performs various control functions. All bits are cleared on reset.
GCR5
General Control Register 5
Offset 0x34
Bit
31
30
29
28
27
26
25
24
—
Type
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
—
Type
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
—
PEX_IRQ_
OUT
OCNDMA1_
POWER
DOWN
OCNDMA1_
DOZE
OCNDMA1_
STOP
—
Type
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
—
OCNDMA0_
POWER
DOWN
OCNDMA0_
DOZE
OCNDMA0_
STOP
—
Type
R/W
Reset
0
0
0
0
0
0
0
0
Table 8-13. GCR5 Bit Descriptions
Name
Reset
Description
Settings
—
31–13
0
Reserved. Write to zero for future compatibility.
PEX_IRQ_
OUT
12
0
PCI Express Message Signal Interrupt
Triggers the PCI Express message signal interrupt.
0
No PCI Express message.
1
PCI Express message
interrupt.
interrupt.
OCNDMA1_
POWER
DOWN
11
0
OCNDMA 1 Complex Power Down
Makes the OCNDMA1 complex power down.
0
OCNDMA1 powered up.
1
OCNDMA1 power down (Stop
ACK).
ACK).
OCNDMA1_
DOZE
10
0
OCNDMA 1 Doze
Used to select Doze mode, in which all register
accesses are acknowledged, but writes are not
written and reads do not contain valid data. Setting
this bit prevents lockup of the device internal bus
while the OCNDMA1 is stopped.
Used to select Doze mode, in which all register
accesses are acknowledged, but writes are not
written and reads do not contain valid data. Setting
this bit prevents lockup of the device internal bus
while the OCNDMA1 is stopped.
0
Normal operation.
1
Doze mode.