Freescale Semiconductor MSC8156 Evaluation Module MSC8156EVM MSC8156EVM Benutzerhandbuch
Produktcode
MSC8156EVM
Detailed Register Descriptions
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
8-23
OCNDMA1_
STOP
9
0
OCNDMA 1 Stop
Makes the OCNDMA1 enter Stop mode.
0
OCNDMA1 normal operation.
1
OCNDMA1 Stop mode.
—
8–4
0
Reserved. Write to zero for future compatibility.
OCNDMA0_
POWER
DOWN
3
0
OCNDMA 0 Complex Power Down
Drives the ips_wait signal to 0 in preparation for
power down to avoid ips transactions becoming
stuck.
Drives the ips_wait signal to 0 in preparation for
power down to avoid ips transactions becoming
stuck.
0
OCNDMA0 powered up.
1
OCNDMA0 power down (Stop
ACK).
ACK).
OCNDMA0_
DOZE
2
0
OCNDMA 0 Doze
Used to select Doze mode, in which all register
accesses are acknowledged, but writes are not
written and reads do not contain valid data. Setting
this bit prevents lockup of the device internal bus
while the OCNDMA0 is stopped.
Used to select Doze mode, in which all register
accesses are acknowledged, but writes are not
written and reads do not contain valid data. Setting
this bit prevents lockup of the device internal bus
while the OCNDMA0 is stopped.
0
Normal operation.
1
Doze mode.
OCNDMA0_
STOP
1
0
OCNDMA 0 Stop
Makes the OCNDMA0 enter Stop mode.
0
OCNDMA0 normal operation.
1
OCNDMA0 Stop mode.
—
0
0
Reserved. Write to zero for future compatibility.
Table 8-13. GCR5 Bit Descriptions (Continued)
Name
Reset
Description
Settings