Freescale Semiconductor MSC8156 Evaluation Module MSC8156EVM MSC8156EVM Benutzerhandbuch
Produktcode
MSC8156EVM
Memory Controller Programming Model
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-77
12.8.17
DDR Initialization Enable (MnDDR_INIT_EN)
The DDR SDRAM initialization enable register provides the enable bit to use the address given
by DDR_INIT_ADDR[INIT_ADDR] for the data to data strobes deskew calibration and for
automatic CAS to preamble calibration during the DDR SDRAM initialization. Table 12-38
describes the DDR_INIT_EN fields.
by DDR_INIT_ADDR[INIT_ADDR] for the data to data strobes deskew calibration and for
automatic CAS to preamble calibration during the DDR SDRAM initialization. Table 12-38
describes the DDR_INIT_EN fields.
Table 12-37. DDR_INIT_ADDR Bit Descriptions
Bit Reset
Description
Settings
INIT_ADDR
31–0
0
Initialization Address
Provides the address used for the data to data strobes skew adjustment and automatic
CAS to preamble calibration after setting DDR_SDRAM_CFG[MEM_EN].
This address is written during the initialization sequence.
Provides the address used for the data to data strobes skew adjustment and automatic
CAS to preamble calibration after setting DDR_SDRAM_CFG[MEM_EN].
This address is written during the initialization sequence.
DDR_INIT_EN
DDR SDRAM Initialization
Offset 0x014C
Enable
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
UIA
—
Type
R/W
R
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
Type
R
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 12-38. DDR_INIT_EN Field Descriptions
Bit Reset
Description
Settings
UIA
31
0
Use Initialization Address
Indicates whether to use the initialization address.
Indicates whether to use the initialization address.
0
Use the default address for training
sequence as calculated by the
controller. This is the first valid
address in the first enabled chip
select.
sequence as calculated by the
controller. This is the first valid
address in the first enabled chip
select.
1
Use the initialization address
programmed in DDR_INIT_ADDR.
programmed in DDR_INIT_ADDR.
—
30–0
0
Reserved. Write to zero for future compatibility.