Freescale Semiconductor MSC8156 Evaluation Module MSC8156EVM MSC8156EVM Benutzerhandbuch

Produktcode

MSC8156EVM

Memory Controller Programming Model

MSC8156 Reference Manual, Rev. 2

Freescale Semiconductor

12-79

RRT

23–20

Read-to-Read Turnaround for Same Chip Select
Specifies how many cycles are added between reads to the same
chip select. If a value of 0000 is chosen, then 2 cycles is required
between read commands to the same chip select if 4-beat bursts are
used (4 cycles are required if 8-beat bursts are used). Note that DDR3
does not support 4-beat bursts. However, this field may be used to
add extra cycles when burst-chop mode is used, and the DDR
controller must wait 4 cycles for read-to-read transactions to the same
chip select.

0000

BL/2 clocks

0001

BL/2 + 1 clock

0010

BL/2 + 2 clocks

0011

BL/2 + 3 clocks

0100

BL/2 + 4 clocks

0101

BL/2 + 5 clocks

0110

BL/2 + 6 clocks

0111

BL/2 + 7 clocks

1000

BL/2 + 8 clocks

1001

BL/2 + 9 clocks

1010

BL/2 + 10 clocks

1011

BL/2 + 11 clocks

1100

BL/2 + 12 clocks

1101

BL/2 + 13 clocks

1110

BL/2 + 14 clocks

1111

BL/2 + 15 clocks

WWT

19–16

Write-to-Write Turnaround for Same Chip Select
Specifies how many cycles are added between writes to the same chip
select. If a value of 0000 is chosen, then 2 cycles is required between
write commands to the same chip select if 4-beat bursts are used (4
cycles are required if 8-beat bursts are used). Note that DDR3 does not
support 4-beat bursts. However, this field may be used to add extra
cycles when burst-chop mode is used, and the DDR controller must
wait 4 cycles for write-to-write transactions to the same chip select.