Analog Devices AD9148 Evaluation Board AD9148-M5372-EBZ AD9148-M5372-EBZ Datenbogen
Produktcode
AD9148-M5372-EBZ
Quick Start Guide
AD9148(-M5372/5)-EBZ
Rev. A | Page 3 of 6
Figure 1
Figure 2
Data Clock Control
This section, shown in
Figure 3, controls the Interpolation Rate and Coarse Modulation. The Modulation Description field will readback the controls selected.
Additionally, the individual half-band filter stages will also update in the respective fields. If an improper selection of these controls is
chosen, the Modulation Description indicator will read Invalid. By default, the AD9516 will automatically update the proper dividers for
the clocks based on the chosen interpolation from the drop-down menu. To disable this feature, select the AD9516 tab and uncheck the
Sync with Interpolation box near the Data Clock controls.
Additionally, the individual half-band filter stages will also update in the respective fields. If an improper selection of these controls is
chosen, the Modulation Description indicator will read Invalid. By default, the AD9516 will automatically update the proper dividers for
the clocks based on the chosen interpolation from the drop-down menu. To disable this feature, select the AD9516 tab and uncheck the
Sync with Interpolation box near the Data Clock controls.
An advanced filter control option is available to manually control the stages of each of the filters. To access this, the Enable Advanced
Filter Control should be turned on. Each of the half-band filters are turned on by their respective enable controls, and the modes for each
filter are set in the corresponding field selections. Note that if the Sync with Interpolation checkbox is selected, the clock dividers will still
be updated according to the interpolation rate selected from the menu, even when using the advanced control.
The Interface Control section of
Figure 3 allows for easy control of the different features that the AD9148 has to offer. Binary Enable controls the number format for the
incoming data with a choice between
unsigned/binary, when enabled, and signed/2’s
compliment, when disabled. When using the
DPG2, the All Ports Enable and One DCI controls
should be selected. Note that the Bus Swap, Byte
Swap, and Q First Enable controls are not supported
features with the DPG2. Byte Mode is supported and
the DPGDownloader panel Interface Mode must be
set to “Byte Mode” for proper execution. When
implementing Byte Mode, the All Ports Enable
control must be disabled (single-port mode
selected) and One DCI must be enabled.
incoming data with a choice between
unsigned/binary, when enabled, and signed/2’s
compliment, when disabled. When using the
DPG2, the All Ports Enable and One DCI controls
should be selected. Note that the Bus Swap, Byte
Swap, and Q First Enable controls are not supported
features with the DPG2. Byte Mode is supported and
the DPGDownloader panel Interface Mode must be
set to “Byte Mode” for proper execution. When
implementing Byte Mode, the All Ports Enable
control must be disabled (single-port mode
selected) and One DCI must be enabled.
Additionally, the clock chip divider must be set
appropriately to allow for a DCO that is twice the
rate of what the setting would be in word mode for
a particular interpolation. Note that byte mode
cannot be used in 1x interpolation mode. For
example, for 2x interpolation using word mode, the
DCO Clk Div Ratio is set to “Divide-by-2”. However, for 2x interpolation using byte mode, the DCO Clk Div Ratio should be set to
“Bypass”. Also, note that the Sync with Interpolation box for the clock divider will not adjust when byte mode is selected and therefore
should be unchecked and the divider set manually in this mode.
appropriately to allow for a DCO that is twice the
rate of what the setting would be in word mode for
a particular interpolation. Note that byte mode
cannot be used in 1x interpolation mode. For
example, for 2x interpolation using word mode, the
DCO Clk Div Ratio is set to “Divide-by-2”. However, for 2x interpolation using byte mode, the DCO Clk Div Ratio should be set to
“Bypass”. Also, note that the Sync with Interpolation box for the clock divider will not adjust when byte mode is selected and therefore
should be unchecked and the divider set manually in this mode.
Figure 3
NCO Control
The NCO controls shown in Figure 4 are listed at the bottom of the “Data” tab, listed previously. When using the NCO, turn the Fine
Modulation control ON and input the DAC Clock rate as well as the NCO Freq Shift (up to ± F
Modulation control ON and input the DAC Clock rate as well as the NCO Freq Shift (up to ± F
dac/2
allowable) and the desired sideband
using Sideband Select. A readback of the calculated FTW
written will appear in the indicator field. Also available is a
phase offset feature for the NCO, which is set through the
NCO Phase Offset Word. For a higher degree of control,
select the Enable Advanced NCO Control while keeping Fine
Modulation ON as well, and use the FTW control to input
written will appear in the indicator field. Also available is a
phase offset feature for the NCO, which is set through the
NCO Phase Offset Word. For a higher degree of control,
select the Enable Advanced NCO Control while keeping Fine
Modulation ON as well, and use the FTW control to input
Figure 4