Analog Devices AD9148 Evaluation Board AD9148-M5372-EBZ AD9148-M5372-EBZ Datenbogen
Produktcode
AD9148-M5372-EBZ
Quick Start Guide
AD9148(-M5372/5)-EBZ
Rev. A | Page 5 of 6
AUX DAC Control
As with the main DACs, the full-scale current of the auxiliary DACs can be set over the SPI port. Each DAC can also be powered down as
well as providing the option to source or sink the current for either the P-side or N-side.
well as providing the option to source or sink the current for either the P-side or N-side.
Sampling Error Detection
The Sampling Error Detection (SED) checks the data inputs. An 8-byte signature is handed to the AD9148. The controller can
automatically generate and load the vectors using the DPG2 device. Indicators display the result of the comparison between the input
data and the expected signature, noting which of the bits contain the errors.
automatically generate and load the vectors using the DPG2 device. Indicators display the result of the comparison between the input
data and the expected signature, noting which of the bits contain the errors.
SPI Map
The SPI Map tab provides an overview of all the settings currently written to the part. The individual register values are indicated
graphically (with red and green boxes) and numerically. The numeric results can be used in whatever system the AD9148 connects to, to
duplicate the current settings in the end system. The SPI Map Read button must be on in order to reflect the current readback of all the
registers. The Read DAC Select control chooses which DAC set values (DAC Set0: DAC1, DAC2 ; DAC Set1: DAC3, DAC4) will appear in
the readback arrays for the duplicated registers.
graphically (with red and green boxes) and numerically. The numeric results can be used in whatever system the AD9148 connects to, to
duplicate the current settings in the end system. The SPI Map Read button must be on in order to reflect the current readback of all the
registers. The Read DAC Select control chooses which DAC set values (DAC Set0: DAC1, DAC2 ; DAC Set1: DAC3, DAC4) will appear in
the readback arrays for the duplicated registers.
AD9516 Control
The evaluation board contains its own clock chip. The AD9516 has an optional on-chip PLL. The top half of the control tab helps the
user select the appropriate control values for the PLL controller. If the PLL is bypassed, the DAC Clock has the same frequency as the
input to the AD9516. Two additional clocks, Ref Clk and DCO Clk, are generated based off of the DAC Clock. The DCO Clock
controlling the data frequency can be synced with the interpolation rate on the Data Clock Control tab. If this is enabled, changing the
interpolation rate will automatically update the AD9516 to have the appropriate DCO Clock Divider Ratio. Note: This is true only for
word mode and is not supported in byte mode, as mentioned previously.
user select the appropriate control values for the PLL controller. If the PLL is bypassed, the DAC Clock has the same frequency as the
input to the AD9516. Two additional clocks, Ref Clk and DCO Clk, are generated based off of the DAC Clock. The DCO Clock
controlling the data frequency can be synced with the interpolation rate on the Data Clock Control tab. If this is enabled, changing the
interpolation rate will automatically update the AD9516 to have the appropriate DCO Clock Divider Ratio. Note: This is true only for
word mode and is not supported in byte mode, as mentioned previously.
Save and Load
The SPI controller has options to save and load all the control registers. The save takes place after the controller is run once and the load
happens before any of the read or writes to the evaluation board.
happens before any of the read or writes to the evaluation board.