Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Datenbogen
Produktcode
AT91SAM9N12-EK
Programmer’s Model
ARM DDI0198D
Copyright © 2001-2003 ARM Limited. All rights reserved.
2-9
Figure 2-2 Cache Type Register format
Ctype
The Ctype field determines the cache type. See Table 2-6.
S bit
Specifies if the cache is a unified cache (S=0), or separate ICache and
DCache (S=1). If S=0, the Isize and Dsize fields both describe the unified
cache and must be identical. In the ARM926EJ-S processor, this bit is set
to a 1 to denote separate caches.
DCache (S=1). If S=0, the Isize and Dsize fields both describe the unified
cache and must be identical. In the ARM926EJ-S processor, this bit is set
to a 1 to denote separate caches.
Dsize
Specifies the size, line length, and associativity of the DCache, or of the
unified cache if the S bit is 0.
unified cache if the S bit is 0.
Isize
Specifies the size, length, and associativity of the ICache, or of the
unified cache if the S bit is 0.
unified cache if the S bit is 0.
The Ctype field specifies if the cache supports lockdown or not, and how it is cleaned.
The encoding is shown in Table 2-6. All unused values are reserved.
The encoding is shown in Table 2-6. All unused values are reserved.
The Dsize and Isize fields in the Cache Type Register have the same format. This is
shown in Figure 2-3.
shown in Figure 2-3.
Figure 2-3 Dsize and Isize field format
Size
The Size field determines the cache size in conjunction with the M bit.
0
31 30 29 28
25 24 23
12 11
0
0 0
Ctype
S
Dsize
Isize
Table 2-6 Ctype encoding
Value
Method
Cache cleaning
Cache lockdown
b1110
Write-back
Register 7 operations
Format C
a
a. See Cache Lockdown Register c9 on page 2-26 for more details on
Format C for cache lockdown.
11 10 9
6 5
3 2 1 0
0 0
Size
Assoc M Len