Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Datenbogen
Produktcode
ATSAM4S-XPLD
936
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
When using a ping-pong endpoint, the following procedures are required to perform Data IN transactions:
1.
The microcontroller checks if it is possible to write in the FIFO by polling TXPKTRDY to be cleared in the end-
point’s UDP_CSRx register.
point’s UDP_CSRx register.
2.
The microcontroller writes the first data payload to be sent in the FIFO (Bank 0), writing zero or more byte values
in the endpoint’s UDP_FDRx register.
in the endpoint’s UDP_FDRx register.
3.
The microcontroller notifies the USB peripheral it has finished writing in Bank 0 of the FIFO by setting the TXPK-
TRDY in the endpoint’s UDP_CSRx register.
TRDY in the endpoint’s UDP_CSRx register.
4.
Without waiting for TXPKTRDY to be cleared, the microcontroller writes the second data payload to be sent in the
FIFO (Bank 1), writing zero or more byte values in the endpoint’s UDP_FDRx register.
FIFO (Bank 1), writing zero or more byte values in the endpoint’s UDP_FDRx register.
5.
The microcontroller is notified that the first Bank has been released by the USB device when TXCOMP in the end-
point’s UDP_CSRx register is set. An interrupt is pending while TXCOMP is being set.
point’s UDP_CSRx register is set. An interrupt is pending while TXCOMP is being set.
6.
Once the microcontroller has received TXCOMP for the first Bank, it notifies the USB device that it has prepared
the second Bank to be sent, raising TXPKTRDY in the endpoint’s UDP_CSRx register.
the second Bank to be sent, raising TXPKTRDY in the endpoint’s UDP_CSRx register.
7.
At this step, Bank 0 is available and the microcontroller can prepare a third data payload to be sent
.
Figure 39-8. Data IN Transfer for Ping-pong Endpoint
Warning: There is software critical path due to the fact that once the second bank is filled, the driver has to wait for
TX_COMP to set TX_PKTRDY. If the delay between receiving TX_COMP is set and TX_PKTRDY is set too long, some
Data IN packets may be NACKed, reducing the bandwidth.
TX_COMP to set TX_PKTRDY. If the delay between receiving TX_COMP is set and TX_PKTRDY is set too long, some
Data IN packets may be NACKed, reducing the bandwidth.
Warning: TX_COMP must be cleared after TX_PKTRDY has been set.
Data IN
Data IN
Read by USB Device
Read by USB Device
Bank 1
Bank 0
FIFO (DPR)
TXCOMP Flag
(UDP_CSRx)
(UDP_CSRx)
Interrupt Cleared by Firmware
Set by USB
Device
Device
TXPKTRDY Flag
(UDP_MCSRx)
(UDP_MCSRx)
ACK
PID
Data IN
PID
ACK
PID
Set by Firmware,
Data Payload Written in FIFO Bank 1
Data Payload Written in FIFO Bank 1
Cleared by USB Device,
Data Payload Fully Transmitted
Data Payload Fully Transmitted
Data IN
PID
USB Bus
Packets
Packets
Set by USB Device
Set by Firmware,
Data Payload Written in FIFO Bank 0
Data Payload Written in FIFO Bank 0
Written by
FIFO (DPR)
Microcontroller
Written by
Microcontroller
Written by
Microcontroller
Microcontroller
Load Data IN Bank 0
Load Data IN Bank 0
Microcontroller Load Data IN Bank 1
USB Device Send Bank 0
USB Device Send Bank 0
Microcontroller Load Data IN Bank 0
USB Device Send Bank 1
USB Device Send Bank 1
Interrupt Pending