Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Datenbogen

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SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 39-10.Bank Swapping in Data OUT Transfers for Ping-pong Endpoints 
When using a ping-pong endpoint, the following procedures are required to perform Data OUT transactions:
1.
The host generates a Data OUT packet.
2.
This packet is received by the USB device endpoint. It is written in the endpoint’s FIFO Bank 0.
3.
The USB device sends an ACK PID packet to the host. The host can immediately send a second Data OUT 
packet. It is accepted by the device and copied to FIFO Bank 1.
4.
The microcontroller is notified that the USB device has received a data payload, polling RX_DATA_BK0 in the end-
point’s UDP_CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK0 is set.
5.
The number of bytes available in the FIFO is made available by reading RXBYTECNT in the endpoint’s 
UDP_CSRx register.
6.
The microcontroller transfers out data received from the endpoint’s memory to the microcontroller’s memory. Data 
received is made available by reading the endpoint’s UDP_FDRx register.
7.
The microcontroller notifies the USB peripheral device that it has finished the transfer by clearing RX_DATA_BK0 
in the endpoint’s UDP_CSRx register.
8.
A third Data OUT packet can be accepted by the USB peripheral device and copied in the FIFO Bank 0.
9.
If a second Data OUT packet has been received, the microcontroller is notified by the flag RX_DATA_BK1 set in 
the endpoint’s UDP_CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK1 is set.
10. The microcontroller transfers out data received from the endpoint’s memory to the microcontroller’s memory. Data 
received is available by reading the endpoint’s UDP_FDRx register.
11. The microcontroller notifies the USB device it has finished the transfer by clearing RX_DATA_BK1 in the end-
point’s UDP_CSRx register.
12. A fourth Data OUT packet can be accepted by the USB device and copied in the FIFO Bank 0.
USB Device
USB Bus
Read
Write
Write and Read at the Same Time
1st Data Payload
2nd Data Payload
3rd Data Payload
3rd Data Payload
2nd Data Payload
1st Data Payload
Data IN Packet
Data IN Packet
Data IN Packet
Microcontroller
Endpoint 1
Bank 0
Endpoint 1
Bank 1
Endpoint 1
Bank 0
Endpoint 1
Bank 0
Endpoint 1
Bank 0
Endpoint 1
Bank 1