Mikroelektronika MikroE Development Kits MIKROE-996 Datenbogen
Produktcode
MIKROE-996
2009-2011 Microchip Technology Inc.
DS39960D-page 97
PIC18F87K22 FAMILY
6.3.4
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. SFRs start at the top of
data memory (FFFh) and extend downward to occupy
all of Bank 15 (F00h to FFFh) and the top part of
Bank 14 (EF4h to EFFh).
A list of these registers is given in
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. SFRs start at the top of
data memory (FFFh) and extend downward to occupy
all of Bank 15 (F00h to FFFh) and the top part of
Bank 14 (EF4h to EFFh).
A list of these registers is given in
and
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
peripheral functions. The Reset and Interrupt registers
are described in their respective chapters, while the
ALU’s STATUS register is described later in this section.
Registers related to the operation of the peripheral
features are described in the chapter for that peripheral.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s.
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
peripheral functions. The Reset and Interrupt registers
are described in their respective chapters, while the
ALU’s STATUS register is described later in this section.
Registers related to the operation of the peripheral
features are described in the chapter for that peripheral.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s.
TABLE 6-1:
SPECIAL FUNCTION REGISTER MAP FOR PIC18F87K22 FAMILY
Addr.
Name
Addr.
Name
Addr.
Name
Addr.
Name
Addr.
Name
Addr.
Name
)
FFFh
TOSU
FDFh
INDF2
(
FBFh ECCP1AS
F9Fh
IPR1
F7Fh
EECON1
F5Fh
RTCCFG
FFEh
TOSH
FDEh POSTINC2
(
)
FBEh ECCP1DEL
F9Eh
PIR1
F7Eh
EECON2
F5Eh
RTCCAL
FFDh
TOSL
FDDh POSTDEC2
)
FBDh
CCPR1H
F9Dh
PIE1
F7Dh
TMR5H
F5Dh
RTCVALH
FFCh
STKPTR
FDCh PREINC2
FBCh
CCPR1L
F9Ch PSTR1CON F7Ch
TMR5L
F5Ch
RTCVALL
FFBh
PCLATU
FDBh PLUSW2
(
FBBh CCP1CON
F9Bh OSCTUNE F7Bh
T5CON
F5Bh
ALRMCFG
FFAh
PCLATH
FDAh
FSR2H
FBAh
PIR5
F9Ah TRISJ
)
F7Ah
T5GCON
F5Ah
ALRMRPT
FF9h
PCL
FD9h
FSR2L
FB9h
PIE5
F99h TRISH
(
)
F79h
CCPR4H
F59h
ALRMVALH
FF8h
TBLPTRU
FD8h
STATUS
FB8h
IPR4
F98h
TRISG
F78h
CCPR4L
F58h
ALRMVALL
FF7h
TBLPTRH
FD7h
TMR0H
FB7h
PIR4
F97h
TRISF
F77h
CCP4CON
F57h CTMUCONH
FF6h
TBLPTRL
FD6h
TMR0L
FB6h
PIE4
F96h
TRISE
F76h
CCPR5H
F56h CTMUCONL
FF5h
TABLAT
FD5h
T0CON
FB5h
CVRCON
F95h
TRISD
F75h
CCPR5L
F55h CTMUICONH
FF4h
PRODH
FD4h SPBRGH1
FB4h
CMSTAT
F94h
TRISC
F74h
CCP5CON
F54h
CM1CON
FF3h
PRODL
FD3h
OSCCON
FB3h
TMR3H
F93h
TRISB
F73h
CCPR6H
F53h
PADCFG1
FF2h
INTCON
FD2h
IPR5
FB2h
TMR3L
F92h
TRISA
F72h
CCPR6L
F52h
ECCP2AS
FF1h
INTCON2
FD1h
WDTCON
FB1h
T3CON
F91h
LATJ
(
F71h
CCP6CON
F51h
ECCP2DEL
FF0h
INTCON3
FD0h
RCON
FB0h
T3GCON
F90h
LATH
(
)
F70h
CCPR7H
F50h
CCPR2H
FEFh
INDF0
(
FCFh
TMR1H
FAFh
SPBRG1
F8Fh
LATG
F6Fh
CCPR7L
F4Fh
CCPR2L
FEEh POSTINC0
(
)
FCEh
TMR1L
FAEh
RCREG1
F8Eh
LATF
F6Eh
CCP7CON
F4Eh
CCP2CON
FEDh POSTDEC0
FCDh
T1CON
FADh
TXREG1
F8Dh
LATE
F6Dh
TMR4
F4Dh
ECCP3AS
FECh PREINC0
FCCh
TMR2
FACh
TXSTA1
F8Ch
LATD
F6Ch
PR4
F4Ch
ECCP3DEL
FEBh PLUSW0
(
FCBh
PR2
FABh
RCSTA1
F8Bh
LATC
F6Bh
T4CON
F4Bh
CCPR3H
FEAh
FSR0H
FCAh
T2CON
FAAh
T1GCON
F8Ah
LATB
F6Ah
SSP2BUF
F4Ah
CCPR3L
FE9h
FSR0L
FC9h
SSP1BUF
FA9h
IPR6
F89h
LATA
F69h
SSP2ADD
F49h
CCP3CON
FE8h
WREG
FC8h SSP1ADD
FA8h HLVDCON
F88h PORTJ
)
F68h
SSP2STAT
F48h
CCPR8H
FE7h
INDF1
(
FC7h SSP1STAT
FA7h
PSPCON
F87h PORTH
(
F67h
SSP2CON1
F47h
CCPR8L
FE6h POSTINC1
(
)
FC6h SSP1CON1
FA6h
PIR6
F86h
PORTG
F66h
SSP2CON2
F46h
CCP8CON
FE5h POSTDEC1
FC5h SSP1CON2
FA5h
IPR3
F85h
PORTF
F65h BAUDCON1
F45h
CCPR9H
)
FE4h PREINC1
FC4h
ADRESH
FA4h
PIR3
F84h
PORTE
F64h
OSCCON2
F44h
CCPR9L
FE3h PLUSW1
(
FC3h
ADRESL
FA3h
PIE3
F83h
PORTD
F63h
EEADRH F43h CCP9CON
)
FE2h
FSR1H
FC2h
ADCON0
FA2h
IPR2
F82h
PORTC
F62h
EEADR F42h CCPR10H
(
FE1h
FSR1L
FC1h
ADCON1
FA1h
PIR2
F81h
PORTB
F61h
EEDATA
F41h CCPR10L
(
FE0h
BSR
FC0h
ADCON2
FA0h
PIE2
F80h
PORTA
F60h
PIE6
F40h CCP10CON
(
Note
1:
This is not a physical register.
2:
Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’.
3:
This register is not available on devices with a program memory of 32 Kbytes (PIC18FX5K22).
4:
Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM. To access these registers,
users must always load the proper BSR value.
users must always load the proper BSR value.