Mikroelektronika MikroE Development Kits MIKROE-996 Datenbogen

Produktcode

MIKROE-996

 2009-2011 Microchip Technology Inc.

DS39960D-page 99

PIC18F87K22 FAMILY

FE6h

POSTINC1

Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)

---- ----

FE5h

POSTDEC1

Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)

---- ----

FE4h

PREINC1

Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)

---- ----

FE3h

PLUSW1

Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) – value of
FSR1 offset by W

---- ----

FE2h

FSR1H

—

Indirect Data Memory Address Pointer 1 High

---- xxxx

FE1h

FSR1L

Indirect Data Memory Address Pointer 1 Low Byte

xxxx xxxx

FE0h

BSR

—

Bank Select Register

---- 0000

FDFh

INDF2

Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)

---- ----

FDEh

POSTINC2

Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)

---- ----

FDDh

POSTDEC2

Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)

---- ----

FDCh

PREINC2

Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)

---- ----

FDBh

PLUSW2

Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) – value of
FSR2 offset by W

---- ----

FDAh

FSR2H

—

Indirect Data Memory Address Pointer 2 High

---- xxxx

FD9h

FSR2L

Indirect Data Memory Address Pointer 2 Low Byte

xxxx xxxx

FD8h

STATUS

—

---x xxxx

FD7h

TMR0H

Timer0 Register High Byte

0000 0000

FD6h

TMR0L

Timer0 Register Low Byte

xxxx xxxx

FD5h

T0CON

TMR0ON

T08BIT

T0CS

T0SE

PSA

TOPS2

TOPS1

TOPS0

1111 1111

FD4h

SPBRGH1

USART1 Baud Rate Generator High Byte

0000 0000

FD3h

OSCCON

IDLEN

IRCF2

IRCF1

IRCF0

OSTS

HFIOFS

SCS1

SCS0

0110 q000

FD2h

IPR5

TMR7GIP

(

)

TMR12IP

(

)

TMR10IP

(

)

TMR8IP

TMR7IP

(

)

TMR6IP

TMR5IP

TMR4IP

1111 1111

FD1h

WDTCON

REGSLP

—

ULPLVL

SRETEN

—

ULPEN

ULPSINK

SWDTEN

0-x0 -000

FD0h

RCON

IPEN

SBOREN

POR

BOR

0111 11qq

FCFh

TMR1H

Timer1 Register High Byte

xxxx xxxx

FCEh

TMR1L

Timer1 Register Low Byte

xxxx xxxx

FCDh

T1CON

TMR1CS1

TMR1CS0

T1CKPS1

T1CKPS0

SOSCEN

T1SYNC

RD16

TMR1ON

0000 0000

FCCh

TMR2

Timer2 Register

0000 0000

FCBh

PR2

Timer2 Period Register

1111 1111

FCAh

T2CON

—

T2OUTPS3 T2OUTPS2

T2OUTPS1

T2OUTPS0

TMR2ON

T2CKPS1

T2CKPS0

-000 0000

FC9h

SSP1BUF

MSSP Receive Buffer/Transmit Register

xxxx xxxx

FC8h

SSP1ADD

MSSP Address Register in I

C™ Slave Mode. SSP1 Baud Rate Reload Register in I

C Master Mode.

0000 0000

FC7h

SSP1STAT

SMP

CKE

D/A

R/W

0000 0000

FC6h

SSP1CON1

WCOL

SSPOV

SSPEN

CKP

SSPM3

SSPM2

SSPM1

SSPM0

0000 0000

FC5h

SSP1CON2

GCEN

ACKSTAT

ACKDT

ACKEN

RCEN

PEN

RSEN

SEN

0000 0000

FC4h

ADRESH

A/D Result Register High Byte

xxxx xxxx

FC3h

ADRESL

A/D Result Register Low Byte

xxxx xxxx

FC2h

ADCON0

—

CHS4

CHS3

CHS2

CHS1

CHS0

GO/DONE

ADON

-000 0000

FC1h

ADCON1

TRIGSEL1

TRIGSEL0

VCFG1

VCFG0

VNCFG

CHSN2

CHSN1

CHSN0

0000 0000

FC0h

ADCON2

ADFM

—

ACQT2

ACQT1

ACQT0

ADCS2

ADCS1

ADCS0

0-00 0000

FBFh

ECCP1AS

ECCP1ASE ECCP1AS2 ECCP1AS1

ECCP1AS0

PSS1AC1

PSS1AC0

PSS1BD1

PSS1BD0

0000 0000

FBEh

ECCP1DEL

P1RSEN

P1DC6

P1DC5

P1DC4

P1DC3

P1DC2

P1DC1

P1DC0

0000 0000

FBDh

CCPR1H

Capture/Compare/PWM Register1 High Byte

xxxx xxxx

FBCh

CCPR1L

Capture/Compare/PWM Register1 Low Byte

xxxx xxxx

FBBh

CCP1CON

P1M1

P1M0

DC1B1

DC1B0

CCP1M3

CCP1M2

CCP1M1

CCP1M0

0000 0000

FBAh

PIR5

TMR7GIF

(

)

TMR12IF

(

)

TMR10IF

(

)

TMR8IF

TMR7IF

(

)

TMR6IF

TMR5IF

TMR4IF

0000 0000

FB9h

PIE5

TMR7GIE

(

)

TMR12IE

(

)

TMR10IE

(

)

TMR8IE

TMR7IE

(

)

TMR6IE

TMR5IE

TMR4IE

0000 0000

FB8h

IPR4

CCP10IP

(

)

CCP9IP

(

)

CCP8IP

CCP7IP

CCP6IP

CCP5IP

CCP4IP

CCP3IP

1111 1111

FB7h

PIR4

CCP10IF

(

)

CCP9IF

(

)

CCP8IF

CCP7IF

CCP6IF

CCP5IF

CCP4IF

CCP3IF

0000 0000

TABLE 6-2:

PIC18F87K22 FAMILY REGISTER FILE SUMMARY (CONTINUED)

Address

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Note 1:

This bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented.

Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’.

Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22).