Intel 1.00 GHz BX80530F1000256 Datenbogen
Produktcode
BX80530F1000256
Datasheet
43
Intel
®
Celeron
®
Processor up to 1.10 GHz
44
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. Not 100% tested. Specified by design characterization.
3. All AC timings for the APIC I/O signals are referenced to the PICCLK rising edge at 0.7 V at the processor
2. Not 100% tested. Specified by design characterization.
3. All AC timings for the APIC I/O signals are referenced to the PICCLK rising edge at 0.7 V at the processor
edge fingers. All APIC I/O signal timings are referenced at 1.25 V at the processor edge fingers.
4. This specification applies to Intel Celeron processors operating with a 66 MHz Intel Celeron processor
system bus only.
5. Referenced to PICCLK rising edge.
6. For open drain signals, valid delay is synonymous with float delay.
7. Valid delay timings for these signals are specified to 2.5 V +5%.
6. For open drain signals, valid delay is synonymous with float delay.
7. Valid delay timings for these signals are specified to 2.5 V +5%.
Table 22. System Bus AC Specifications (APIC Clock and APIC I/O) at the Processor Edge
Fingers (for S.E.P. Package)
T# Parameter
Min
Max
Unit
Figure
Notes
T21’: PICCLK Frequency
2.0
33.3
MHz
T22’: PICCLK Period
30.0
500.0
ns
T23’: PICCLK High Time
12.0
ns
T24’: PICCLK Low Time
12.0
ns
T25’: PICCLK Rise Time
0.25
3.0
ns
T26’: PICCLK Fall Time
0.25
3.0
ns
T27’: PICD[1:0] Setup Time
8.5
ns
5
T28’: PICD[1:0] Hold Time
3.0
ns
5
T29’: PICD[1:0] Valid Delay
3.0
12.0
ns
5, 6, 7