Intel 1.00 GHz BX80530F1000256 Datenbogen
Produktcode
BX80530F1000256
Datasheet
45
Intel
®
Celeron
®
Processor up to 1.10 GHz
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Celeron processors at all frequencies.
2. These specifications are tested during manufacturing.
3. All AC timings for the APIC I/O signals are referenced to the PICCLK rising edge at 1.25 V at the processor
2. These specifications are tested during manufacturing.
3. All AC timings for the APIC I/O signals are referenced to the PICCLK rising edge at 1.25 V at the processor
pins. All APIC I/O signal timings are referenced at 0.75 V at the processor pins.
4. Referenced to PICCLK rising edge.
5. For open drain signals, valid delay is synonymous with float delay.
6. Valid delay timings for these signals are specified into 150
5. For open drain signals, valid delay is synonymous with float delay.
6. Valid delay timings for these signals are specified into 150
Ω
load pulled up to 1.5 V.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Intel
®
Celeron
®
processor frequencies.
2. All AC timings for the TAP signals are referenced to the TCK rising edge at 0.70 V at the processor edge
fingers. All TAP signal timings (TMS, TDI, etc.) are referenced at 1.25 V at the processor edge fingers.
3. Not 100% tested. Specified by design characterization.
4. 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16.667 MHz.
5. Referenced to TCK rising edge.
6. Referenced to TCK falling edge.
7. Valid delay timing for this signal is specified to 2.5 V +5%.
8. Non-Test Outputs and Inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO, and
4. 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16.667 MHz.
5. Referenced to TCK rising edge.
6. Referenced to TCK falling edge.
7. Valid delay timing for this signal is specified to 2.5 V +5%.
8. Non-Test Outputs and Inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO, and
TMS). These timings correspond to the response of these signals due to TAP operations.
9. During Debug Port operation, use the normal specified timings rather than the TAP signal timings.
Table 24. System Bus AC Specifications (APIC Clock and APIC I/O)
1, 2, 3
T# Parameter
Min
Max
Unit
Figure
Notes
T21: PICCLK Frequency
2.0
33.3
MHz
T22: PICCLK Period
30.0
500.0
ns
T23: PICCLK High Time
10.5
ns
@ > 1.7 V
T24: PICCLK Low Time
10.5
ns
@ < 0.7 V
T25: PICCLK Rise Time
0.25
3.0
ns
(0.7 V–1.7 V)
T26: PICCLK Fall Time
0.25
3.0
ns
(1.7 V–0.7 V)
T27: PICD[1:0] Setup Time
5.0
ns
4
T28: PICD[1:0] Hold Time
2.5
ns
4
T29a: PICD[1:0] Valid Delay (Rising Edge)
1.5
8.7
ns
4, 5, 6
T29b: PICD[1:0] Valid Delay (Falling Edge)
1.5
12.0
ns
4, 5, 6
Table 25. System Bus AC Specifications (TAP Connection) at the Processor Edge Fingers
(For S.E.P. Package)
T# Parameter
Min
Max
Unit
Figure
Notes
T30’: TCK Frequency
16.667
MHz
T31’: TCK Period
60.0
ns
T32’: TCK High Time
25.0
ns
@1.7 V
T33’: TCK Low Time
25.0
ns
@0.7 V
T34’: TCK Rise Time
5.0
ns
(0.7 V–1.7 V)
4
T35’: TCK Fall Time
5.0
ns
(1.7 V–0.7 V)
4
T36’: TRST# Pulse Width
40.0
ns
Asynchronous
T37’: TDI, TMS Setup Time
5.5
ns
5
T38’: TDI, TMS Hold Time
14.5
ns
5
T39’: TDO Valid Delay
2.0
13.5
ns
6, 7
T40’: TDO Float Delay
28.5
ns
6, 7
T41’: All Non-Test Outputs Valid Delay
2.0
27.5
ns
6, 8, 9
T42’: All Non-Test Inputs Setup Time
27.5
ns
6, 8, 9
T43’: All Non-Test Inputs Setup Time
5.5
ns
5, 8, 9
T44’: All Non-Test Inputs Hold Time
14.5
ns
5, 8, 9