Intel U1300 LE80538UE0042M Datenbogen

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 Specification 

Update 

Under certain conditions as described in the IA-32 Intel® Architecture Software 

Developers Manual, section titled Out-of-Order Stores for String Operations in 

Pentium® 4, Intel® Xeon®, and P6 Family Processors, the processor performs REP 

MOVS or REP STOS as fast strings. Due to this erratum, fast string REP MOVS/REP 

STOS instructions that cross page boundaries from WB/WC memory types to 

UC/WP/WT memory types, may start using an incorrect data size or may observe 

memory ordering violations. 

Implication:  Upon crossing the page boundary the following may occur, dependent on the new 

page memory type: 

• 

UC the data size of each write will now always be 8 bytes, as opposed to the 

original data size. 

• 

WP the data size of each write will now always be 8 bytes, as opposed to the 

original data size and there may be a memory ordering violation. 

• 

WT there may be a memory ordering violation. 

Workaround: Software should avoid crossing page boundaries from WB or WC memory type to UC, 

WP or WT memory type within a single REP MOVS or REP STOS instruction that will 

execute with fast strings enabled.

 

For the steppings affected, see the 

Summary Tables of Changes

In the event that software implements memory aliasing by having two Page Directory 

Entries (PDEs) point to a common Page Table Entry (PTE) and the Accessed and Dirty 

bits for the two PDEs are allowed to become inconsistent the processor may become 

deadlocked. 

Implication:  This erratum has not been observed with commercially-available software. 

Workaround: Software that needs to implement memory aliasing in this way should manage the 

consistency of the Accessed and Dirty bits. 

For the steppings affected, see the 

Summary Tables of Changes

.