Intel U1300 LE80538UE0042M Datenbogen
Produktcode
LE80538UE0042M
Errata
Specification Update
21
AE6.
VM Bit Is Cleared on Second Fault Handled by Task Switch from
Virtual-8086 (VM86)
Problem:
Following a task switch to any fault handler that was initiated while the processor
was in VM86 mode, if there is an additional fault while servicing the original task
switch then the VM bit will be incorrectly cleared in EFLAGS, data segments will not
be pushed and the processor will not return to the correct mode upon completion of
the second fault handler via IRET.
Implication: When the OS recovers from the second fault handler, the processor will no longer be
in VM86 mode. Normally, operating systems should prevent interrupt task switches
from faulting, thus the scenario should not occur under normal circumstances.
Workaround: None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes
.
AE7.
Page with PAT (Page Attribute Table) Set to USWC (Uncacheable
Speculative Write Combine) While Associated MTRR (Memory Type
Range Register) Is UC (Uncacheable) May Consolidate to UC
Problem:
A page whose PAT memory type is USWC while the relevant MTRR memory type is
UC, the consolidated memory type may be treated as UC (rather than WC, as
specified in IA-32 Intel® Architecture Software Developer's Manual).
Implication: When this erratum occurs, the memory page may be as UC (rather than WC). This
may have a negative performance impact.
Workaround: None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes
.
AE8.
FPU Operand Pointer May Not Be Cleared following FINIT/FNINIT
Problem:
Initializing the floating point state with either FINIT or FNINT, may not clear the x87
FPU Operand (Data) Pointer Offset and the x87 FPU Operand (Data) Pointer Selector
(both fields form the FPUDataPointer). Saving the floating point environment with
FSTENV, FNSTENV, or floating point state with FSAVE, FNSAVE or FXSAVE before an
intervening FP instruction may save uninitialized values for the FPUDataPointer.
Implication: When this erratum occurs, the values for FPUDataPointer in the saved floating point
image structure may appear to be random values. Executing any non-control FP
instruction with memory operand will initialize the FPUDataPointer. Intel has not
observed this erratum with any commercially-available software.
Workaround: After initialization, do not expect a floating point state saved memory image to be
correct, until at least one non-control FP instruction with a memory operand has been
executed.
Status:
For the steppings affected, see the
Summary Tables of Changes
.