Intel D2500 DF8064101055400 Datenbogen

Datasheet - Volume 1 of 2

21

DDR3_ODTPU

This signal needs to be terminated to VSS on board using 

the RES of 275 ohms. This external resistor termination 

scheme is used for Resistor compensation of DDR ODT 

strength.

O

Analog

DDR3_DQPU

This signal needs to be terminated to VSS on board using 

the RES of 35 ohms. This external resistor termination 

scheme is used for Resistor compensation of DQ buffers

O

Analog

DDR3_CMDPU

This signal needs to be terminated to VSS on board using 

the RES. This external resistor termination scheme is 

used for Resistor compensation of CMD buffers. 

O

Analog

DDR3_VREF

DDR interface Reference Voltage

I

Analog

DDR3_DRAM_PWROK This signal indicates the status of 1.5-V power supply.

I

Asynchronous 

CMOS

DDR3_MON1P
DDR3_MON1N
DDR3_MON2P
DDR3_MON2N

These signals are for internal electrical validation. They 

do not carry functionality on customer platform

O

CMOS

DDR3_REFP
DDR3_REFN

100MHz Differential Board clock input for DDR PLL.

I

Differential 

Clock

DDR3_DRAMRST#

Asynchronous output Reset signal to the DRAM devices. 

It is common to all ranks.

O

DDR3

PWROK/ 

DDR3_VCCA_PWROK

PowerOK: Asserted once the VRM is settled. Used primarily in 

the DDR PHY to determine S3.

I

CMOS

HPLL_REFCLK_P,
HPLL_REFCLK_N

Differential refclk for the Intel Atom Processor D2000 series and 

N2000 series processor's HPLL. The “_P” signal corresponds to 

the rising edge of the internal clock. 100 MHz. 100 MHz

I

CMOS