Intel D2500 DF8064101055400 Datenbogen
Produktcode
DF8064101055400
Datasheet - Volume 1 of 2
41
3.2.4.2
LVDS Pair States
The LVDS pairs can be put into one of five states:
•
Active
•
Powered down tri-state
•
Powered down 0-V
•
Send zeros
When in the active state, several data formats are supported. When in powered down
state, the circuit enters a low power state and drives out 0-V or tri-states on both the
output pins for the entire channel. When in the send zeros state, the circuit is powered
up but sends only zero for the pixel color data regardless what the actual data is with
the clock lines and timing signals sending the normal clock and timing data.
The LVDS Port can be enabled/disabled using software. A disabled port enters a low
power state. Once the port is enabled, individual driver pairs may be disabled based on
the operating mode. Disabled drivers can be powered down for reduced power
consumption or optionally fixed to forced 0s output.
Individual pairs or sets of LVDS pairs can be selectively powered down when not being
used. The panel power sequencing can be set to override the selected power state of
the drivers during power sequencing.
3.2.4.3
Single Channel Mode
In Single Channel mode, Channel A can take 18 bits of RGB pixel data, plus 3 bits of
timing control (HSYNC/VSYNC/DE) and output them on three differential data pair
outputs; or 24 bits of RGB (plus 4 bits of timing control) output on four differential data
pair outputs. A dual channel interface converts 36 or 48 bits of color information plus
the 3 or 4 bits of timing control respectively and outputs it on six or eight sets of
differential data outputs respectively.
Note:
Platforms using the ICH for integrated graphics support 24 bpp display panels of Type 1
only (compatible with VESA LVDS color mapping).
Figure 3-3. LVDS Clock and Data Relationship