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2.9.7
Monitoring Activity in the MMC/SD Mode
2.9.7.1
Determining Whether New Data is Available in MMCDRR
2.9.7.2
Verifying that MMCDXR is Ready to Accept New Data
2.9.7.3
Checking for CRC Errors
2.9.7.4
Checking for Time-Out Events
2.9.7.5
Determining When a Response/Command is Done
2.9.7.6
Determining Whether the Memory Card is Busy
2.9.7.7
Determining Whether a Data Transfer is Done
Peripheral Architecture
This section describes registers and specific register bits that you can use to obtain the status of the
MMC/SD controller in the MMC/SD mode. You can determine the status of the MMC/SD controller by
reading the bits in the MMC status register 0 (MMCST0) and MMC status register 1 (MMCST1).
MMC/SD controller in the MMC/SD mode. You can determine the status of the MMC/SD controller by
reading the bits in the MMC status register 0 (MMCST0) and MMC status register 1 (MMCST1).
The MMC/SD controller sets the DRRDY bit in MMCST0 when the data in the FIFO is greater than the
threshold set in the MMC FIFO control register (MMCFIFOCTL). If the interrupt request is enabled
(EDRRDY = 1 in MMCIM), the ARM is notified of the event by an interrupt. A read of the MMC data
receive register (MMCDDR) clears the DRRDY flag.
threshold set in the MMC FIFO control register (MMCFIFOCTL). If the interrupt request is enabled
(EDRRDY = 1 in MMCIM), the ARM is notified of the event by an interrupt. A read of the MMC data
receive register (MMCDDR) clears the DRRDY flag.
The MMC/SD controller sets the DXRDY bit in MMCST0 when the amount of data in the FIFO is less than
the threshold set in the MMC FIFO control register (MMCFIFOCTL). If the interrupt request is enabled
(EDXRDY = 1 in MMCIM), the ARM is notified of the event by an interrupt.
the threshold set in the MMC FIFO control register (MMCFIFOCTL). If the interrupt request is enabled
(EDXRDY = 1 in MMCIM), the ARM is notified of the event by an interrupt.
The MMC/SD controller sets the CRCRS, CRCRD, and CRCWR bits in MMCST0 in response to the
corresponding CRC errors of command response, data read, and data write. If the interrupt request is
enabled (ECRCRS/ECRCRD/ECRCWR = 1 in MMCIM), the ARM is notified of the CRC error by an
interrupt.
corresponding CRC errors of command response, data read, and data write. If the interrupt request is
enabled (ECRCRS/ECRCRD/ECRCWR = 1 in MMCIM), the ARM is notified of the CRC error by an
interrupt.
The MMC/SD controller sets the TOUTRS and TOUTRD bits in MMCST0 in response to the
corresponding command response or data read time-out event. If the interrupt request is enabled
(ETOUTRS/ETOUTRD = 1 in MMCIM), the ARM is notified of the event by an interrupt.
corresponding command response or data read time-out event. If the interrupt request is enabled
(ETOUTRS/ETOUTRD = 1 in MMCIM), the ARM is notified of the event by an interrupt.
The MMC/SD controller sets the RSPDNE bit in MMCST0 when the response is done; or in the case of
commands that do not require a response, when the command is done. If the interrupt request is enabled
(ERSPDNE = 1 in MMCIM), the ARM is also notified.
commands that do not require a response, when the command is done. If the interrupt request is enabled
(ERSPDNE = 1 in MMCIM), the ARM is also notified.
The card sends a busy signal either when waiting for an R1b-type response or when programming the last
write data into its flash memory. The MMC/SD controller has two flags to notify you whether the memory
card is sending a busy signal. The two flags are complements of each other:
write data into its flash memory. The MMC/SD controller has two flags to notify you whether the memory
card is sending a busy signal. The two flags are complements of each other:
•
The BSYDNE flag in MMCST0 is set if the card did not send or is not sending a busy signal when the
MMC/SD controller is expecting a busy signal (BSYEXP = 1 in MMCCMD). The interrupt by this bit is
enabled by a corresponding interrupt enable bit (EBSYDNE = 1 in MMCIM).
MMC/SD controller is expecting a busy signal (BSYEXP = 1 in MMCCMD). The interrupt by this bit is
enabled by a corresponding interrupt enable bit (EBSYDNE = 1 in MMCIM).
•
The BUSY flag in MMCST1 is set when a busy signal is received from the card.
The MMC/SD controller sets the DATDNE bit in MMCST0 when all of the bytes of a data transfer have
been transmitted/received. The DATDNE bit is polled to determine when to stop writing to the data
transmit register (for a write operation) or when to stop reading from the data receive register (for a read
operation). The ARM is also notified of the time-out event by an interrupt if the interrupt request is enabled
(EDATDNE = 1 in MMCIM).
been transmitted/received. The DATDNE bit is polled to determine when to stop writing to the data
transmit register (for a write operation) or when to stop reading from the data receive register (for a read
operation). The ARM is also notified of the time-out event by an interrupt if the interrupt request is enabled
(EDATDNE = 1 in MMCIM).
SPRUE30B – September 2006
Multimedia Card (MMC)/Secure Digital (SD) Card Controller
25