Benutzerhandbuch für Texas Instruments TMS320DM644x

Inhaltsverzeichnis

• Table of Contents

  3
• Preface

  7
• 1 Introduction

  9
  • 1.1 Purpose of the Peripheral

    9
  • 1.2 Features

    9
  • 1.3 Functional Block Diagram

    9
  • 1.4 Supported Use Case Statement

    10
  • 1.5 Industry Standard(s) Compliance Statement

    10
• 2 Peripheral Architecture

  10
  • 2.1 Clock Control

    12
  • 2.2 Signal Descriptions

    13
  • 2.3 Protocol Descriptions

    13
    • 2.3.1 MMC/SD Mode Write Sequence

      13
    • 2.3.2 MMC/SD Mode Read Sequence

      14
  • 2.4 Data Flow in the Input/Output FIFO

    15
  • 2.5 Data Flow in the Data Registers (MMCDRR and MMCDXR)

    17
  • 2.6 FIFO Operation During Card Read Operation

    19
    • 2.6.1 EDMA Reads

      19
    • 2.6.2 CPU Reads

      19
  • 2.7 FIFO Operation During Card Write Operation

    21
    • 2.7.1 EDMA Writes

      21
    • 2.7.2 CPU Writes

      21
  • 2.8 Reset Considerations

    23
    • 2.8.1 Software Reset Considerations

      23
    • 2.8.2 Hardware Reset Considerations

      23
  • 2.9 Initialization

    23
    • 2.9.1 MMC/SD Controller Initialization

      23
    • 2.9.2 Initializing the MMC Control Register (MMCCTL)

      23
    • 2.9.3 Initializing the Clock Controller Registers (MMCCLK)

      24
    • 2.9.4 Initialize the Interrupt Mask Register (MMCIM)

      24
    • 2.9.5 Initialize the Time-Out Registers (MMCTOR and MMCTOD)

      24
    • 2.9.6 Initialize the Data Block Registers (MMCBLEN and MMCNBLK)

      24
    • 2.9.7 Monitoring Activity in the MMC/SD Mode

      25
      • 2.9.7.1 Determining Whether New Data is Available in MMCDRR

        25
      • 2.9.7.2 Verifying that MMCDXR is Ready to Accept New Data

        25
      • 2.9.7.3 Checking for CRC Errors

        25
      • 2.9.7.4 Checking for Time-Out Events

        25
      • 2.9.7.5 Determining When a Response/Command is Done

        25
      • 2.9.7.6 Determining Whether the Memory Card is Busy

        25
      • 2.9.7.7 Determining Whether a Data Transfer is Done

        25
      • 2.9.7.8 Determining When Last Data has Been Written to Card (SanDisk SD cards)

        26
      • 2.9.7.9 Checking For a Data Transmit Empty Condition

        26
      • 2.9.7.10 Checking for a Data Receive Full Condition

        26
      • 2.9.7.11 Checking the Status of the SD_CLK Pin

        26
      • 2.9.7.12 Checking the Remaining Block Count During a Multiple-Block Transfer

        26
  • 2.10 Interrupt Support

    27
    • 2.10.1 Interrupt Events and Requests

      27
    • 2.10.2 Interrupt Multiplexing

      27
  • 2.11 DMA Event Support

    28
  • 2.12 Power Management

    28
  • 2.13 Emulation Considerations

    28
• 3 Procedures for Common Operations

  29
  • 3.1 Card Identification Operation

    29
    • 3.1.1 MMC Card Identification Procedure

      29
    • 3.1.2 SD Card Identification Procedure

      30
  • 3.2 MMC/SD Mode Single-Block Write Operation Using CPU

    32
  • 3.3 MMC/SD Mode Single-Block Write Operation Using the EDMA

    34
  • 3.4 MMC/SD Mode Single-Block Read Operation Using the CPU

    34
  • 3.5 MMC/SD Mode Single-Block Read Operation Using EDMA

    35
  • 3.6 MMC/SD Mode Multiple-Block Write Operation Using CPU

    36
  • 3.7 MMC/SD Mode Multiple-Block Write Operation Using EDMA

    38
  • 3.8 MMC/SD Mode Multiple-Block Read Operation Using CPU

    38
  • 3.9 MMC/SD Mode Multiple-Block Read Operation Using EDMA

    39
• 4 Registers

  40
  • 4.1 MMC Control Register (MMCCTL)

    41
  • 4.2 MMC Memory Clock Control Register (MMCCLK)

    42
  • 4.3 MMC Status Register 0 (MMCST0)

    43
  • 4.4 MMC Status Register 1 (MMCST1)

    45
  • 4.5 MMC Interrupt Mask Register (MMCIM)

    46
  • 4.6 MMC Response Time-Out Register (MMCTOR)

    47
  • 4.7 MMC Data Read Time-Out Register (MMCTOD)

    48
  • 4.8 MMC Block Length Register (MMCBLEN)

    49
  • 4.9 MMC Number of Blocks Register (MMCNBLK)

    50
  • 4.10 MMC Number of Blocks Counter Register (MMCNBLC)

    50
  • 4.11 MMC Data Receive Register (MMCDRR)

    51
  • 4.12 MMC Data Transmit Register (MMCDXR)

    51
  • 4.13 MMC Command Register (MMCCMD)

    52
  • 4.14 MMC Argument Register (MMCARGHL)

    54
  • 4.15 MMC Response Registers (MMCRSP0-MMCRSP7)

    55
  • 4.16 MMC Data Response Register (MMCDRSP)

    57
  • 4.17 MMC Command Index Register (MMCCIDX)

    57
  • 4.18 MMC FIFO Control Register (MMCFIFOCTL)

    58
• Appendix A Revision History

  59