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4.3
MMC Status Register 0 (MMCST0)
Registers
The MMC status register 0 (MMCST0) records specific events or errors. The transition from 0 to 1 on each
bit in MMCST0 can cause an interrupt signal to be sent to the CPU. If an interrupt is desired, set the
corresponding interrupt enable bit in the MMC interrupt mask register (MMCIM).
bit in MMCST0 can cause an interrupt signal to be sent to the CPU. If an interrupt is desired, set the
corresponding interrupt enable bit in the MMC interrupt mask register (MMCIM).
In most cases, when a status bit is read, it is cleared. The two exceptions are the DRRDY bit and the
DXRDY bit; these bits are cleared only in response to the functional events described for them in
DXRDY bit; these bits are cleared only in response to the functional events described for them in
or in response to a hardware reset.
The MMC status register 0 (MMCST0) is shown in
and described in
.
Figure 20. MMC Status Register 0 (MMCST0)
31
16
Reserved
R-0
15
13
12
11
10
9
8
Reserved
TRNDNE
DATED
DRRDY
DXRDY
Reserved
R-0
R-0
RC-0
R-0
R-1
R-0
7
6
5
4
3
2
1
0
CRCRS
CRCRD
CRCWR
TOUTRS
TOUTRD
RSPDNE
BSYDNE
DATDNE
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; RC = Cleared to 0 when read; -n = value after reset
Table 8. MMC Status Register 0 (MMCST0) Field Descriptions
Bit
Field
Value
Description
31-13
Reserved
0
Reserved
12
TRNDNE
Transfer done.
0
No data transfer is done.
1
Data transfer of specified length is done.
11
DATED
DAT3 edge detected. DATED is cleared when read by CPU.
0
A DAT3 edge has not been detected.
1
A DAT3 edge has been detected.
10
DRRDY
Data receive ready. DRRDY is cleared to 0 when the DAT logic is reset (DATRST = 1 in MMCCTL),
when a command is sent with data receive/transmit clear (DCLR = 1 in MMCCMD), or when data is
read from the MMC data receive register (MMCDRR).
when a command is sent with data receive/transmit clear (DCLR = 1 in MMCCMD), or when data is
read from the MMC data receive register (MMCDRR).
0
MMCDRR is not ready.
1
MMCDRR is ready. New data has arrived and can be read by the CPU or by the DMA controller.
9
DXRDY
Data transmit ready. DXRDY is set to 1 when the DAT logic is reset (DATRST = 1 in MMCCTL), when a
command is sent with data receive/transmit clear (DCLR = 1 in MMCCMD), or when data is written to
the MMC data transmit register (MMCDXR).
command is sent with data receive/transmit clear (DCLR = 1 in MMCCMD), or when data is written to
the MMC data transmit register (MMCDXR).
0
MMCDXR is not ready.
1
MMCDXR is ready. The data in MMCDXR has been transmitted; MMCDXR can accept new data from
the CPU or from the DMA controller.
the CPU or from the DMA controller.
8
Reserved
0
Reserved
7
CRCRS
Response CRC error.
0
A response CRC error has not been detected.
1
A response CRC error has been detected.
6
CRCRD
Read-data CRC error.
0
A read-data CRC error has not been detected.
1
A read-data CRC error has been detected.
SPRUE30B – September 2006
Multimedia Card (MMC)/Secure Digital (SD) Card Controller
43