Texas Instruments TURBO-DECODER COPROCESSOR 2 TMS320C6457 DSP Benutzerhandbuch
6.25 TCP2 Status Register (TCPSTAT)
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Registers
The TCP2 status register (TCPSTAT) is shown in
and described in
Figure 55. TCP2 Status Register (TCPSTAT)
31
28
27
24
Reserved
TCP_STATE
R-0
R-0
23
22
21
20
16
CRC_PASS
SNR_EXCEED
ACTIVE_ITER
R-0
R-0
R-0
15
12
11
10
9
8
ACTIVE_
ACTIVE_STATE
EMUHALT
ROP
RHD
MAP
R-0
R-0
R-0
R-0
R-0
7
6
5
4
3
2
1
0
REXT
WAP
WSP
WINT
WIC
ERR
DEC_BUSY
Reserved
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 30. TCP2 Status Register (TCPSTAT) Field Descriptions
Bit
Field
Value
Description
31-28
Reserved
0
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
27-24
TCP_STATE
TCP2 top level state of state machine. The states are defined in the TCP2 state machine section.
23
CRC_PASS
CRC status
0
CRC has not passed
1
CRC passed
22-21
SNR_EXCEED
SNR status
0
0 MAP0 failed SNR
0
1 MAP0 passed SNR
1
0 MAP1 failed SNR
1
1 MAP1 passed SNR
20-16
ACTIVE_ITER
Active TCP2 iteration status.
15-12
ACTIVE_STATE
Active state status
11
ACTIVE_MAP
Active map status
Note: ACTIVE_MAP bit status is reserved when the FREE bit = 0 and the SOFT bit = 0.
10
EMUHALT
Defines if the TCP2 is halted due to emulation.
0
Not halted due to emulation
1
Halted due to emulation
Note: EMUHALT bit status is reserved when the FREE bit = 0 and the SOFT bit = 1.
9
ROP
Defines if the TCP2 is waiting for output parameter data to be read.
0
Not waiting
1
Waiting for RAM output registers to be read
8
RHD
Defines if the TCP2 is waiting for hard decision data to be read.
0
Not waiting
1
Waiting for RAM output/decision memory to be read
SPRUGK1 – March 2009
TMS320C6457 Turbo-Decoder Coprocessor 2
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