Benutzerhandbuch für Texas Instruments TURBO-DECODER COPROCESSOR 2 TMS320C6457 DSP

Inhaltsverzeichnis

• Table of Contents

  3
• Preface

  8
• 1 Features

  9
• 2 Introduction

  10
• 3 Overview

  11
• 4 Standalone (SA) Mode

  12
  • 4.1 Input Data Format

    13
    • 4.1.1 Systematic and Parity Data

      13
    • 4.1.2 Interleaver Indexes

      16
  • 4.2 Output Decision Data Format

    16
  • 4.3 Stopping Criteria

    16
  • 4.4 Stopping Test Unit

    17
    • 4.4.1 SNR Threshold Termination

      17
    • 4.4.2 CRC Termination

      17
    • 4.4.3 Parameter Termination

      18
      • 4.4.3.1 Maximum Iterations

        18
      • 4.4.3.2 Minimum Iterations

        18
• 5 Shared-Processing (SP) Mode

  18
  • 5.1 Input Data Format

    22
    • 5.1.1 Systematic and Parity Data

      22
    • 5.1.2 A Priori Data

      24
  • 5.2 Output Data Format

    24
• 6 Registers

  25
  • 6.1 Peripheral Identification Register (PID)

    27
  • 6.2 TCP2 Input Configuration Register 0 (TCPIC0)

    28
  • 6.3 TCP2 Input Configuration Register 1 (TCPIC1)

    29
  • 6.4 TCP2 Input Configuration Register 2 (TCPIC2)

    29
  • 6.5 TCP2 Input Configuration Register 3 (TCPIC3)

    30
  • 6.6 TCP2 Input Configuration Register 4 (TCPIC4)

    31
  • 6.7 TCP2 Input Configuration Register 5 (TCPIC5)

    32
  • 6.8 Tail Symbols

    32
  • 6.9 TCP2 Input Configuration Register 6 (TCPIC6)

    33
  • 6.10 TCP2 Input Configuration Register 7 (TCPIC7)

    34
  • 6.11 TCP2 Input Configuration Register 8 (TCPIC8)

    35
  • 6.12 TCP2 Input Configuration Register 9 (TCPIC9)

    36
  • 6.13 TCP2 Input Configuration Register 10 (TCPIC10)

    37
  • 6.14 TCP2 Input Configuration Register 11 (TCPIC11)

    37
  • 6.15 TCP2 Input Configuration Register 12 (TCPIC12)

    39
  • 6.16 TCP2 Input Configuration Register 13 (TCPIC13)

    39
  • 6.17 TCP2 Input Configuration Register 14 (TCPIC14)

    40
  • 6.18 TCP2 Input Configuration Register 15 (TCPIC15)

    41
  • 6.19 TCP2 Output Parameter Register 0 (TCPOUT0)

    42
  • 6.20 TCP2 Output Parameter Register 1 (TCPOUT1)

    42
  • 6.21 TCP2 Output Parameter Register 2 (TCPOUT2)

    43
  • 6.22 TCP2 Execution Register (TCPEXE)

    43
  • 6.23 TCP2 Endian Register (TCPEND)

    44
  • 6.24 TCP2 Error Register (TCPERR)

    45
  • 6.25 TCP2 Status Register (TCPSTAT)

    47
  • 6.26 TCP2 Emulation Register (TCPEMU)

    49
• 7 Endianness

  50
  • 7.1 Data Memory for Systematic

    50
    • 7.1.1 Hard Decision Data

      53
    • 7.1.2 TCP_ENDIAN Register for Endianness Manager

      54
    • 7.1.3 Interleaver Data

      55
      • 7.1.3.1 ENDIAN_INTR = 1

        55
      • 7.1.3.2 ENDIAN_INTR = 0

        56
    • 7.1.4 Extrinsic Data

      57
      • 7.1.4.1 ENDIAN_EXTR = 1

        57
      • 7.1.4.2 ENDIAN_EXTR = 0

        59
• 8 Architecture

  59
  • 8.1 Sub-block and Sliding Window Segmentation

    60
  • 8.2 Subframe Segmentation (SP mode only)

    61
  • 8.3 Reliability and Prolog Length Calculation

    62
  • 8.4 Added Features

    63
    • 8.4.1 Code Rates

      63
    • 8.4.2 Input Sign

      64
    • 8.4.3 Log Equation

      64
    • 8.4.4 Re-Encode

      64
• 9 Programming

  64
  • 9.1 EDMA3 Resources

    65
    • 9.1.1 TCP2 Dedicated EDMA3 Resources

      65
    • 9.1.2 Special TCP2 EDMA3 Programming Considerations

      65
  • 9.2 Programming Standalone (SA) Mode

    66
    • 9.2.1 EDMA3 Programming

      66
      • 9.2.1.1 Input Configuration Parameters Transfer

        66
      • 9.2.1.2 Systematics and Parities Transfer

        66
      • 9.2.1.3 Interleaver Indexes Transfer

        67
      • 9.2.1.4 Hard-Decisions Transfer

        68
      • 9.2.1.5 Output Parameters Transfer

        69
    • 9.2.2 Input Configurations Parameters Programming

      69
  • 9.3 Programming Shared-Processing (SP) Mode

    70
    • 9.3.1 EDMA3 Programming

      71
      • 9.3.1.1 Input Configuration Parameters Transfer

        71
      • 9.3.1.2 Systematics and Parities Transfer

        71
      • 9.3.1.3 A Priori Transfer

        72
      • 9.3.1.4 Extrinsics Transfer

        73
    • 9.3.2 Input Configurations Parameters Programming

      73
• 10 Output Parameters

  74
• 11 Events Generation

  74
• 12 Debug Mode: Pause After Each Map

  75
• 13 Errors and Status

  75
  • 13.1 Errors

    75
    • 13.1.1 Error Status: ERR

      75
    • 13.1.2 Unexpected Frame Length: F

      76
    • 13.1.3 Unexpected Prolog Length: P

      76
    • 13.1.4 Unexpected Subframe Length: SF

      76
    • 13.1.5 Unexpected Reliability Length: R

      76
    • 13.1.6 Unexpected Signal to Noise Ratio: SNR

      76
    • 13.1.7 Unexpected Interleaver Table Load: INT

      76
    • 13.1.8 Unexpected Output Parameters Load: OP

      76
    • 13.1.9 Unexpected Memory Access: ACC

      76
    • 13.1.10 Unexpected Max and Min Iterations: MAXMINITER

      77
  • 13.2 Status

    77
    • 13.2.1 TCP2 Decoder Status: dec_busy

      77
    • 13.2.2 TCP2 Stopped Due to Error: ERR

      77
    • 13.2.3 TCP2 Waiting for Input Control Parameters Write: WIC

      77
    • 13.2.4 TCP2 Waiting for Interleaver Table Write: WINT

      77
    • 13.2.5 TCP2 Waiting for Systematics and Parities Write: WSP

      77
    • 13.2.6 TCP2 Waiting for A prioris Write: WAP

      77
    • 13.2.7 TCP2 Waiting for Extrinsics Read: REXT

      77
    • 13.2.8 TCP2 Waiting for Hard-Decisions Read: RHD

      77
    • 13.2.9 TCP2 Waiting for Output Parameters Read: ROP

      77
    • 13.2.10 TCP2 Halted Due to Emulation: emuhalt

      77
    • 13.2.11 TCP2 Active Map status: Active_map

      77
    • 13.2.12 TCP2 Active State Status: Active_state

      78
    • 13.2.13 TCP2 Active Iteration Status: Active_iter

      78
    • 13.2.14 TCP2 SNR Status: snr_exceed

      78
    • 13.2.15 TCP2 CRC Status: Crc_pass

      78
    • 13.2.16 TCP2 State: TCP_STATE

      78